scholarly journals DESIGN AND INVESTIGATION OF 65 NM RF CMOS TECHNOLOGY LC-VCO’S / AUKŠTADAŽNIŲ, 65 NM KMOP TECHNOLOGIJOS, LC ĮTAMPA VALDOMŲ GENERATORIŲ PROJEKTAVIMAS IR TYRIMAS

2014 ◽  
Vol 6 (2) ◽  
pp. 198-201 ◽  
Author(s):  
Vytautas Mačaitis ◽  
Vaidotas Barzdėnas
Keyword(s):  
Power Dissipation ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Rf Cmos ◽  
Voltage Controlled Oscillators ◽  
Capacitor Array ◽  
Layout Area ◽  
Offset Frequency

In this paper, two LC Voltage-Controlled Oscillators (LC-LC-VCO1 and LC-VCO2) are designed using TSMC 65 nm LP/MS/RF CMOS technology. Two arrays, one of which is a 6-bit capacitor array and the other – an array of MOS varactors, provide a wide LC-VCO frequency tuning range. Post-layout simulation results unveiled that at 1.8 V supply voltage the tuning range of LC-VCO1 spans from 5.17 GHz to 6.76 GHz and for LC-VCO2 the range spans from 6.33 GHz to 8.08 GHz. The phase noise at 1 MHz offset frequency is about −123.1 dBc/Hz for LC-VCO1 and −121.6 dBc/Hz for LC-VCO2. The power dissipation at maximum carrier is 30.47 mW for LC-VCO1 and 30.5 mW for LC-VCO2. The layout area is 285×335 μm and 255×305 μm, respectively for LC-VCO1 and LC-VCO2. Straipsnyje nagrinėjami ir projektuojami LC įtampa valdomi generatoriai (LC-ĮVG), plačiai taikomi šiuolaikiniuose daugiastandarčiuose ir daugiajuosčiuose siųstuvuose-imtuvuose. Naudojant TSMC kompanijos 65 nm LP/MS/RF KMOP inte­grinių grandynų gamybos technologiją suprojektuoti ir išanalizuoti du skirtingų dažnio diapazonų LC-ĮVG. Generuojamas dažnis yra valdomas dviem būdais, t. y. galimas apytikslis bei tikslus dažnio nustatymas. Norint apytiksliai nustatyti dažnį naudojamas 6 bitais skaitmeniškai valdomas perjungiamų kondensatorių blokas, o norint tiksliai parinkti valdymą – NMOP varaktorių blokas. Kompiuterinio modeliavimo metu gauti tokie pagrindiniai LC-ĮVG parametrai: valdomo dažnio diapazonas – nuo 5,17 GHz iki 6,76 GHz (LC-ĮVG1) ir nuo 6,33 GHz iki 8,08 GHz (LC-ĮVG2); fazinis triukšmas, esant 1 MHz poslinkio dažniui ir maksimaliam nešlio dažniui: –123,1 dBc/Hz (LC-ĮVG1) ir –121,6 dBc/Hz (LC-ĮVG2); vartojamoji galia, esant maksimaliam nešlio dažniui: –30,47 mW (LC-ĮVG1) ir 30,5 mW (LC-ĮVG2). Suprojektuotų LC-ĮVG1 ir LC-ĮVG2 topologijų plotas yra atitinkamai lygus 0,078 mm2 ir 0,096 mm2.

scholarly journals Analysis of Main LC-VCO Parameters for Multistandard Tranceivers

2017 ◽  
Vol 9 (3) ◽  
pp. 324-328 ◽  
Author(s):  
Vytautas Mačaitis ◽  
Romualdas Navickas
Keyword(s):  
Power Supply ◽  
Carrier Frequency ◽  
Power Dissipation ◽  
Figure Of Merit ◽  
Tuning Range ◽  
Supply Voltage ◽  
Quality Function ◽  
Voltage Controlled Oscillators ◽  
Cmos Ic ◽  
Ic Technology

This paper reviews CMOS LC Voltage Controlled Oscillators (VCO) for wireless multi-standard transceivers and wireless communications. The main parameters, such as IC technology, phase noise, carrier frequency, supply voltage, tuning range, power dissipation, figure of merit (FOMT and FOMTT) were reviewed in this paper. These parameters were taken of 20 articles published in 2012–2016 years. Of the reviewed articles it can be said that most VCOs was designed in 180 nm (55%) and 65 nm (25%) CMOS IC technology. FOMTT quality function has been proposed for extended VCO quality assessment. FOMTT quality function additionally evaluates VCO IC technology, and the power supply.

scholarly journals Design of area-efficient GHz range current mode frequency synthesizer using standard CMOS technology

2019 ◽  
Vol 70 (4) ◽  
pp. 323-328
Author(s):  
Dan-Dan Zheng ◽  
Yu-Bin Li ◽  
Chang-Qi Wang ◽  
Kai Huang ◽  
Xiao-Peng Yu
Keyword(s):  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Mode Frequency ◽  
Loop Filter ◽  
Silicon Area ◽  
Power Efficient ◽  
A Current

Abstract In this paper, an area and power efficient current mode frequency synthesizer for system-on-chip (SoC) is proposed. A current-mode transformer loop filter suitable for low supply voltage is implemented to remove the need of a large capacitor in the loop filter, and a current controlled oscillator with additional voltage based frequency tuning mechanism is designed with an active inductor. The proposed design is further integrated with a fully programmable frequency divider to maintain a good balance among output frequency operating range, power consumption as well as silicon area. A test chip is implemented in a standard 0.13 µm CMOS technology, measurement result demonstrates that the proposed design has a working range from 916 MHz to 1.1 l GHz and occupies a silicon area of 0.25 mm2 while consuming 8.4 mW from a 1.2 V supply.

scholarly journals Analysis On Power Gating Circuits Based Low Power VLSI Circuits (BCD Adder)

2021 ◽  
Vol 2089 (1) ◽  
pp. 012080
Author(s):  
M. Srinivas ◽  
K.V. Daya Sagar
Keyword(s):  
Energy Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Leakage Power ◽  
Vlsi Circuits ◽  
Battery Life

Abstract Currently, energy consumption in the digital circuit is a key design parameter for emerging mobile products. The principal cause of the power dissipation during idle mode is leakage currents, which are rising dramatically. Sub-threshold leakage is increased by the scaling of threshold voltage when gate current leakage increases because oxide thickness is scaled. With rising demands for mobile devices, leakage energy consumption has received even greater attention. Since a mobile device spends most of its time in standby mode, leakage power savings need to prolong the battery life. That is why low power has become a significant factor in CMOS circuit design. The required design and simulation of an AND gate with the BSIM4 MOS parameter model at 27 0C, supply voltage of 0,70V with CMOS technology of 65nm are the validation of the suitability of the proposed circuit technology. AND simulation. The performance parameters for the two AND input gate are compared with the current MTCMOS and SCCMOS techniques, such as sub-threshold leakage power dissipations in active and standby modes, the dynamic dissipation, and propagation period. The proposed hybrid super cutoff complete stack technique compared to the current MTCMOS technology shows a reduction in sub-threshold dissipation power dissipation by 3. 50x and 1.15x in standby modes and active modes respectively. The hybrid surface-cutting technique also shows savings of 2,50 and 1,04 in power dissipation at the sub-threshold in standby modes and active modes compared with the existing SCCMOS Technique.

scholarly journals Floating Active Inductor Based Trans-Impedance Amplifier in 0.18 μm CMOS Technology for Optical Applications

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1547
Author(s):  
Xiangyu Chen ◽  
Yasuhiro Takahashi
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Chip Area ◽  
Active Inductors ◽  
Low Pass ◽  
Optical Applications ◽  
Fifth Order

In this paper, a transimpedance amplifier (TIA) based on floating active inductors (FAI) is presented. Compared with conventional TIAs, the proposed TIA has the advantages of a wider bandwidth, lower power dissipation, and smaller chip area. The schematics and characteristics of the FAI circuit are explained. Moreover, the proposed TIA employs the combination of capacitive degeneration, the broadband matching network, and the regulated cascode input stage to enhance the bandwidth and gain. This turns the TIA design into a fifth-order low pass filter with Butterworth response. The TIA is implemented using 0.18 μ m Rohm CMOS technology and consumes only 10.7 mW with a supply voltage of 1.8 V. When used with a 150 fF photodiode capacitance, it exhibits the following characteristics: gain of 41 dB Ω and −3 dB frequency of 10 GHz. This TIA occupies an area of 180 μ m × 118 μ m.

Design methodology for a switching-mode RF CMOS power amplifier with an output transformer

2015 ◽  
Vol 8 (3) ◽  
pp. 471-477
Author(s):  
Changhyun Lee ◽  
Changkun Park
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Design Methodology ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Rf Cmos ◽  
Power Transistor ◽  
Voltage Output ◽  
Switching Mode ◽  
Output Transformer

In this study, we propose a design methodology for a switching-mode RF CMOS power amplifier with an output transformer. For a given supply voltage, output power, and target efficiency, the initial values of the transistor size, output inductance, and capacitance can be sequentially determined during the design of the power amplifier. The breakdown voltage of the power transistor is considered in the design methodology. To prove the feasibility of the proposed design methodology, we provide the design example of a 2.4-GHz switching-mode CMOS power amplifier with 180-nm RF CMOS technology. From the measured results, the feasibility of the proposed design methodology is proved.

scholarly journals Estimation of Leakage Power and Delay in CMOS Circuits

2020 ◽  
Vol 4 (7) ◽  
pp. 14-19
Author(s):  
Mohasinul Huq N Md ◽  
Mohan Das S ◽  
Bilal N Md
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Full Adder ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Leakage Power ◽  
Nand Gate ◽  
High Threshold ◽  
Cmos Circuits ◽  
Low Leakage

This paper presents an estimation of leakage power and delay for 1-bit Full Adder (FA)designed which is based on Leakage Control Transistor (LCT) NAND gates as basic building block. The main objective is to design low leakage full adder circuit with the help of low and high threshold transistors. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. The saving in leakage power dissipation for LCT NAND_HVT gate is up to 72.33% and 45.64% when compared to basic NAND and LCT NAND gate. Similarly for 1-bit full adder the saving is up to 90.9% and 40.08% when compared to basic NAND FA and LCT NAND.

A low-voltage 40-GHz complementary VCO with 15% frequency tuning range in SOI CMOS technology

2004 ◽  
Vol 39 (5) ◽  
pp. 841-846 ◽  
Author(s):  
Neric Fong ◽  
Jonghae Kim ◽  
J.-O. Plouchart ◽  
N. Zamdmer ◽  
Duixian Liu ◽  
...  
Keyword(s):  
Tuning Range ◽  
Low Voltage ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Soi Cmos

scholarly journals A Design of Wide-Range and Low Phase Noise Linear Transconductance VCO with 193.76 dBc/Hz FoMT for mm-Wave 5G Transceivers

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 935 ◽  
Author(s):  
Arash Hejazi ◽  
YoungGun Pu ◽  
Kang-Yoon Lee
Keyword(s):  
Phase Noise ◽  
Carrier Frequency ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Process ◽  
Switched Capacitor ◽  
Voltage Controlled Oscillator ◽  
Wide Range ◽  
Layout Area ◽  
Low Phase Noise

This paper presents a wide-range and low phase noise mm-Wave Voltage Controlled Oscillator (VCO) based on the transconductance linearization technique. The proposed technique eliminates the deep triode region of the active part of the VCO, and lowers the noise introduced by the gm-cell. The switch sizes inside the switched capacitor bank of the VCO are optimized to minimize the resistance of the switches while keeping the wide tuning range. A new layout technique shortens the routing of the VCO outputs, and lowers the parasitic inductance and resistance of the VCO routing. The presented method prevents the reduction of the quality factor of the tank due to the long routing. The proposed VCO achieves a discrete frequency tuning range, of 14 GHz to 18 GHz, through a linear coarse and middle switched capacitor array, and offers superior phase noise performance compared to recent state-of-the-art VCO architectures. The design is implemented in a 45 nm CMOS process and occupies a layout area (including output buffers) of 0.14 mm2. The power consumption of the VCO core is 24 mW from the power supply of 0.8 V. The post-layout simulation result shows the VCO achieves the phase noise performances of −87.2 dBc/Hz and −113 dBc/Hz, at 100 kHz and 1 MHz offset frequencies from the carrier frequency of 14 GHz, respectively. In an 18 GHz carrier frequency, the results are −87.4 dBc/Hz and −110 dBc/Hz, accordingly.

A 0.015-mm $^{\text{2}}$ Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology

2017 ◽  
Vol 64 (6) ◽  
pp. 655-659 ◽  
Author(s):  
Gyu-Seob Jeong ◽  
Wooseok Kim ◽  
Jaejin Park ◽  
Taeik Kim ◽  
Hojin Park ◽  
...  
Keyword(s):  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Clock Generator ◽  
28 Nm

Low Phase Noise Voltage Controlled Oscillator Using Cascode and Current-Reuse Techniques for Radio Frequency Circuits

2013 ◽  
Vol 479-480 ◽  
pp. 513-516
Author(s):  
Shuo Chang Hsu ◽  
Meng Ting Hsu ◽  
Yu Tuan Hsu
Keyword(s):  
Phase Noise ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Building Blocks ◽  
Voltage Controlled Oscillator ◽  
Ieee 802.11A ◽  
Current Reuse ◽  
Chip Fabrication ◽  
Offset Frequency ◽  
Low Phase Noise

The voltage-controlled-oscillator (VCO) is one of the most important building blocks in the system. The chip fabrication of VCO is made by TSMC 0.18μm 1P6M CMOS standard process. The chip presents a low power and low phase noise for IEEE 802.11a applications, the PMOS casecode and current-reuse cross-couple technology are designed to improve phase noise and reduce power. The measured results of phase noise is-120.87 dBc/Hz at 1MHz offset frequency from the carrier frequency 5.05 GHz, and operates frequency from 5.04 GHz to 5.895 GHz with a tuning range of 17.14%. Under supply voltage 1.65V, the core power dissipation is 4.05 mW.

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