ANALYSIS OF A NOVEL FULL ADDER DESIGNED FOR IMPLEMENTING IN CARBONE NANOTUBE TECHNOLOGY

A novel low power-delay product full adder circuit is presented in this paper. A new approach is used in order to design full-swing full adder with low number of transistors. The proposed full adder is implemented in MOSFET-like Carbon nanotube technology and the layout is provided based on standard 32 nm technology from MOSIS. The simulation results using HSPICE show that, there are substantial improvements in both power and performance of the proposed circuit compared to latest designs. In addition, the proposed circuit has been implemented in conventional 32 nm process to estimate the advantages of using carbon-based transistors in digital designs over conventional silicon technology. The proposed circuit can be applied in ultra low power and very high speed applications.

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Design and Analysis of a New Carbon Nanotube Full Adder Cell

Journal of Nanomaterials ◽

10.1155/2011/906237 ◽

2011 ◽

Vol 2011 ◽

pp. 1-6 ◽

Cited By ~ 12

Author(s):

M. H. Ghadiry ◽

Asrulnizam Abd Manaf ◽

M. T. Ahmadi ◽

Hatef Sadeghi ◽

M. Nadi Senejani

Keyword(s):

Carbon Nanotube ◽

High Performance ◽

Full Adder ◽

Cmos Technology ◽

Ultra Low Power ◽

And Performance ◽

Carbon Nanotube Technology ◽

Power Delay Product ◽

Full Swing ◽

Very High

A novel full adder circuit is presented. The main aim is to reduce power delay product (PDP) in the presented full adder cell. A new method is used in order to design a full-swing full adder cell with low number of transistors. The proposed full adder is implemented in MOSFET-like carbon nanotube technology and the layout is provided based on standard 32 nm technology from MOSIS. The simulation results using HSPICE show that there are substantial improvements in both power and performance of the proposed circuit compared to the latest designs. In addition, the proposed circuit has been implemented in conventional 32 nm process to compare the benefits of using MOSFET-like carbon nanotubes in arithmetic circuits over conventional CMOS technology. The proposed circuit can be applied in very high performance and ultra-low-power applications.

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Design a Low Power and High Speed 130nm Fulladder using Exclusive-OR and Exclusive NOR Gates

International Journal of Innovative Technology and Exploring Engineering - Special Issue ◽

10.35940/ijitee.e8659.0310521 ◽

2021 ◽

Vol 10 (5) ◽

pp. 81-86

Author(s):

Soniya Nuthalapati ◽

Ranjitha P.V.Sai ◽

Radhika Rani Kalapala ◽

Lourdu Sasi Rekha Lingisetty ◽

Sirisha Mekala ◽

...

Keyword(s):

Low Power ◽

Composite Structures ◽

High Speed ◽

Full Adder ◽

Power Requirement ◽

Pass Transistor ◽

Power Delay Product ◽

Exclusive Or ◽

Full Swing ◽

Design Power

This literature illustrates the high speed and low power Full Adder (FADD) designs. This study relates to the composited structure of FADD design composed in one unit. In this the EXCL-OR/EXCL-NOR designs are used to design the FADD. Mostly concentrates on high speed standard FADD structure by combining the EXCL-OR/EXCL-NOR design in single unit. We implemented two composite structures of FADD through the full swing EXCL-OR/EXCL-NOR designs. And the EXCL-OR/EXCL-NOR design is done through pass transistor logic (PTL) and the same design projected on the composited FADD design. Such that the delay, area of the design, power requirement for the circuit gets optimized. The two composited FADD designs are compared and reduced the constraints of power requirement, area, delay and the power delay product (PDP). The simulated outcomes are verified through 130nnm CMOS mentor graphics tool.

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Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) ◽

10.2174/2352096513666200107091932 ◽

2020 ◽

Vol 13 (6) ◽

pp. 864-870

Author(s):

Sai Venkatramana Prasada G.S ◽

G. Seshikala ◽

S. Niranjana

Keyword(s):

Low Power ◽

Power Dissipation ◽

High Speed ◽

High Performance ◽

Full Adder ◽

Fundamental Operation ◽

Wallace Tree ◽

Power Delay Product ◽

The Comparative Study ◽

Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

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High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

International Journal of Advanced Research in Science, Communication and Technology ◽

10.48175/ijarsct-1845 ◽

2021 ◽

pp. 263-269

Author(s):

Tejaswini M. L ◽

Aishwarya H ◽

Akhila M ◽

B. G. Manasa

Keyword(s):

High Speed ◽

High Performance ◽

Full Adder ◽

Cmos Technology ◽

Power Performance ◽

High Speed Design ◽

Power Delay Product ◽

Full Swing ◽

Output Swing ◽

High Output

The main aim of our work is to achieve low power, high speed design goals. The proposed hybrid adder is designed to meet the requirements of high output swing and minimum power. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of XOR-XNOR circuit. In hybrid FAs maximum power is consumed by XOR-XNOR circuit. In this paper 10T XOR-XNOR is proposed, which provide good driving capabilities and full swing output simultaneously without using any external inverter. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. This circuit outperforms its counterparts showing power delay product is reduced than that of available XOR-XNOR modules. Four different full adder designs are proposed utilizing 10T XOR-XNOR, sum and carry modules. The proposed FAs provide improvement in terms of PDP than that of other architectures. To evaluate the performance of proposed full adder circuit, we embedded it in a 4-bit and 8-bit cascaded full adder. Among all FAs two of the proposed FAs provide the best performance for a higher number of bits.

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Design and Performance Analysis of 1-Bit FinFET Full Adder Cells for Subthreshold Region at 16 nm Process Technology

Journal of Nanomaterials ◽

10.1155/2015/726175 ◽

2015 ◽

Vol 2015 ◽

pp. 1-13 ◽

Cited By ~ 3

Author(s):

‘Aqilah binti Abdul Tahrim ◽

Huei Chaeng Chin ◽

Cheng Siong Lim ◽

Michael Loong Peng Tan

Keyword(s):

High Speed ◽

Average Power ◽

Full Adder ◽

Propagation Delay ◽

Oxide Semiconductor ◽

Process Technology ◽

Subthreshold Region ◽

And Performance ◽

Power Delay Product ◽

20 Nm

The scaling process of the conventional 2D-planar metal-oxide semiconductor field-effect transistor (MOSFET) is now approaching its limit as technology has reached below 20 nm process technology. A new nonplanar device architecture called FinFET was invented to overcome the problem by allowing transistors to be scaled down into sub-20 nm region. In this work, the FinFET structure is implemented in 1-bit full adder transistors to investigate its performance and energy efficiency in the subthreshold region for cell designs of Complementary MOS (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission Gate (TG), and Hybrid CMOS (HCMOS). The performance of 1-bit FinFET-based full adder in 16-nm technology is benchmarked against conventional MOSFET-based full adder. The Predictive Technology Model (PTM) and Berkeley Shortchannel IGFET Model-Common Multi-Gate (BSIM-CMG) 16 nm low power libraries are used. Propagation delay, average power dissipation, power-delay-product (PDP), and energy-delay-product (EDP) are analysed based on all four types of full adder cell designs of both FETs. The 1-bit FinFET-based full adder shows a great reduction in all four metric performances. A reduction in propagation delay, PDP, and EDP is evident in the 1-bit FinFET-based full adder of CPL, giving the best overall performance due to its high-speed performance and good current driving capabilities.

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DESIGN AND ANALYSIS OF A NOVEL LOW PDP FULL ADDER CELL

Journal of Circuits System and Computers ◽

10.1142/s0218126611007323 ◽

2011 ◽

Vol 20 (03) ◽

pp. 439-445 ◽

Cited By ~ 9

Author(s):

M. H. GHADIRY ◽

ABU KHARI A'AIN ◽

M. NADI S.

Keyword(s):

Power Consumption ◽

Low Power ◽

High Performance ◽

Full Adder ◽

Cmos Technology ◽

Accurate Analysis ◽

And Performance ◽

Full Swing ◽

Driving Capability

This paper, presents a new full-swing low power high performance full adder circuit in CMOS technology. It benefits from a full swing XOR-XNOR module with no feedback transistors, which decreases delay and power consumption. In addition, high driving capability of COUT module and low PDP design of SUM module contribute to more PDP reduction in cascaded mode. In order to have accurate analysis, the new circuit along with several well-known full adders from literature have been modeled and compared with CADENCE. Comparison consists of power consumption, performance, PDP, and area. Results show that there are improvements in both power consumption and performance. This design trades area with low PDP.

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Gate Diffusion Input Based 10-T CNTFET Power Efficient Full Adder

Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) ◽

10.2174/2352096514666210106094136 ◽

2021 ◽

Vol 14 ◽

Author(s):

Priyanka Tyagi ◽

Sanjay Kumar Singh ◽

Piyush Dua

Keyword(s):

High Speed ◽

Full Adder ◽

Additional Advantage ◽

Power Efficient ◽

Digital World ◽

Diffusion Technique ◽

Low Power Dissipation ◽

Power Delay Product ◽

The Comparative Study ◽

Full Swing

Background: Full adder is the key element of the digital electronics. The CNTFET is the most promising device in modern electronics. To enhance the performance of the full adder CNTFET is used in place of the CMOS. Objective: To implement the high speed full adder circuit for advance applications of the digital world. Methods: Full adder circuit with new Gate diffusion technique has been implemented in this work. There is the comparative study of the 10-T CNTFET full adder with GDI technique and the 10-T Finfet based full adder using GDI technique. Ultralow power feature is the additional advantage of the GDI technique. This technology provides the full swing voltage to the circuit moreover it also reduces number of transistors required. This technique has been used with CNTFET to upgrade full adder in terms of the dissipated power and product of power consumed and delay introduced in the circuit. Results: The proposed design shows that the low power dissipation comes out to be approximately 4.3nW at 0.5volts. The power delay product is 4.7x10-20 J at the same voltage level. The Finfet design also shows the better performance with GDI. But GDI enhance CNTFET based design power consumption about 32% from the FinFET. Conclusions: CNTFET observed the better response due to good current conductivity as compare to the FinFET. This work has been implemented and simulated on the 32nm node technology.

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