RESIDUE-WEIGHTED NUMBER CONVERSION FOR MODULI SET {2n-1, 2n + 1, 22n + 1, 2n} USING SIGNED-DIGIT NUMBER

2013 ◽  
Vol 22 (01) ◽  
pp. 1250070
Author(s):  
CHANGJUN JIANG ◽  
SHUGANG WEI

Signed-digit number systems support carry-free, constant time addition. By introducing the signed-digit number arithmetic into a residue number system (RNS), arithmetic operations can be performed efficiently. In this paper, a new algorithm for residue-to-binary conversion for four moduli set {2n-1, 2n + 1, 22n + 1, 2n} that only requires modulo 24n - 1 SD number addition is proposed. This moduli set has 5n-bit dynamic range. Based on the proposed algorithm, the converters are designed with a two-level binary tree structure formed by the modulo 24n - 1 SD number residue adders. Moreover, we simplify the residue adders in converters to obtain more area and time efficiency. The comparison of the converters proposed with the converter using binary arithmetic using 0.18 μm CMOS gate array technology yields reductions in delays of 44%, 60% and 75% for n = 4, n = 8 and n = 16, respectively.

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1113
Author(s):  
Shang Ma ◽  
Shuai Hu ◽  
Zeguo Yang ◽  
Xuesi Wang ◽  
Meiqing Liu ◽  
...  

The Residue Number System (RNS) is a non-weighted number system. Benefiting from its inherent parallelism, RNS has been widely studied and used in Digital Signal Processing (DSP) systems and cryptography. However, since the dynamic range in RNS has been fixed by its moduli set, it is hard to solve the overflow problem, which can be easily solved in Two’s Complement System (TCS) by expanding the bit-width of it. For the multiplication in RNS, the traditional way to deal with overflow is to scale down the inputs so that the result can fall in its dynamic range. However, it leads to a loss of precision. In this paper, we propose a high-precision RNS multiplier for three-moduli set 2n−1,2n,2n+1, which is the most used moduli set. The proposed multiplier effectively improves the calculation precision by adding several compensatory items to the result. The compensatory items can be obtained directly from preceding scalers with little extra effort. To the best of our knowledge, we are the first one to propose a high-precision RNS multiplier for the moduli set 2n−1,2n,2n+1. Simulation results show that the proposed RNS multiplier can get almost the same calculation precision as the TCS multiplier with respect to Mean Square Error (MSE) and Signal-to-Noise Ratio(SNR), which outperforms the basic scaling RNS multiplier about 2.6–3 times with respect to SNR.


2020 ◽  
Vol 29 (11) ◽  
pp. 2030008
Author(s):  
Raj Kumar ◽  
Ritesh Kumar Jaiswal ◽  
Ram Awadh Mishra

Modulo multiplier has been attracting considerable attention as one of the essential components of residue number system (RNS)-based computational circuits. This paper contributes a comprehensive review in the design of modulo [Formula: see text] multipliers for the first time. The modulo multipliers can be implemented using ROM (look-up-table) as well as VLSI components (memoryless); however, the former is preferable for lower word-length and later for larger word-length. The modular and parallelism properties of RNS are used to improve the performance of memoryless multipliers. Moreover, a Booth-encoding algorithm is used to speed-up the multipliers. Also, an advanced modulo [Formula: see text] multiplier based on redundant RNS (RRNS) could be further chosen for very high dynamic range. These perspectives of modulo [Formula: see text] multipliers have been extensively studied for recent state-of-the-art and analyzed using Synopsis design compiler tool.


2000 ◽  
Vol 10 (01n02) ◽  
pp. 85-99 ◽  
Author(s):  
A. P VINOD ◽  
A. BENJAMIN PREMKUMAR

This paper presents a residue number system to binary converter in the four moduli set {2n - 1, 2n, 2n + 1, 2n + 1 - 1}, valid for even values of n. This moduli set is an extension of the popular set {2n - 1, 2n + 1}. The number theoretic properties of the moduli set of the form 2n ± 1 are exploited to design the converter. The main challenge of dealing with fractions in Residue Number System is overcome by using the fraction compensation technique. A hardware implementation using only adders is also proposed. When compared to the common three moduli reverse converters, this four moduli converter offers a larger dynamic range and higher parallelism, which makes it useful for high performance computing.


2020 ◽  
Author(s):  
Tao Wu

Abstract Modular exponentiation is fundamental in computer arithmetic and is widely applied in cryptography such as ElGamal cryptography, Diffie-Hellman key exchange protocol, and RSA cryptography. Implementation of modular exponentiation in residue number system leads to high parallelism in computation, and has been applied in many hardware architectures. While most RNS based architectures utilizes RNS Montgomery algorithm with two residue number systems, the recent modular multiplication algorithm with sum-residues performs modular reduction in only one residue number system with about the same parallelism. In this work, it is shown that high-performance modular exponentiation and RSA cryptography can be implemented in RNS. Both the algorithm and architecture are improved to achieve high performance with extra area overheads, where a 1024-bit modular exponentiation can be completed in 0.567 ms in Xilinx XC6VLX195t-3 platform, costing 26,489 slices, 87,357 LUTs, 363 dedicated multipilers of $18\times 18$ bits, and 65 Block RAMs.


2022 ◽  
Vol 12 (1) ◽  
pp. 463
Author(s):  
Mikhail Babenko ◽  
Anton Nazarov ◽  
Maxim Deryabin ◽  
Nikolay Kucherov ◽  
Andrei Tchernykh ◽  
...  

Error detection and correction codes based on redundant residue number systems are powerful tools to control and correct arithmetic processing and data transmission errors. Decoding the magnitude and location of a multiple error is a complex computational problem: it requires verifying a huge number of different possible combinations of erroneous residual digit positions in the error localization stage. This paper proposes a modified correcting method based on calculating the approximate weighted characteristics of modular projections. The new procedure for correcting errors and restoring numbers in a weighted number system involves the Chinese Remainder Theorem with fractions. This approach calculates the rank of each modular projection efficiently. The ranks are used to calculate the Hamming distances. The new method speeds up the procedure for correcting multiple errors and restoring numbers in weighted form by an average of 18% compared to state-of-the-art analogs.


2017 ◽  
Vol 2 (6) ◽  
pp. 25-30 ◽  
Author(s):  
Alhassan Abdul- Barik ◽  
Mohammed Ibrahim Daabo ◽  
Stephen Akobre

The greatest difficulty of compressing data is the assurance of the security, integrity, and accuracy of the data in storage in volatile media or transmission in network communication channels. Various methods have been proposed for dealing with the accuracy and consistency of compressed and encrypted data using error detection and correction mechanisms. The Redundant Residue Number System (RRNS) which is a trait of Residue Number System (RNS) is one of the available methods for detecting and correcting errors which involves the addition of extra moduli called redundant moduli. In this paper, Residue Number System (RNS) is efficiently applied to the Lempel-Ziv-Welch (LZW) compression algorithm resulting in new LZW-RNS compression scheme using the traditional moduli set, and two redundant moduli added resulting in the moduli set {2^n-1,〖 2〗^n,〖 2〗^n+1,〖 2〗^2n-3,〖 2〗^2n+1} for the purposes of error detection and correction. This is done by constraining the data or information within the legitimate range of the dynamic range provided by the non-redundant moduli. Simulation with MatLab shows the efficiency and fault tolerance of the proposed scheme than the traditional LZW compression method and other related known state of the art schemes.


2016 ◽  
Vol 29 (1) ◽  
pp. 101-112
Author(s):  
Ivan Krstic ◽  
Negovan Stamenkovic ◽  
Vidosav Stojanovic

A binary-to-residues encoder (forward encoder) is an essential building block for the residue number system digital signal processing (RNS DSP) and as such it should be built with a minimal amount of hardware and be efficient in terms of speed and power. The main parts of the forward encoder are residue generators which are usually classified into two categories: the one based on arbitrary moduli-set which make use of look-up tables, and the other based on the special moduli sets. A new memory less architecture of binary-to-RNS encoder based on the special moduli set {2n?1,2n,2n+1} with embedded modulo 2n+1 channel in the diminished-1 representation is presented. Any of two channels (standard modulo 2n +1, or modulo 2n+1 in the diminished-1 representation) operation can be performed by using a single switch. The proposed encoder has been implemented on a Xilinx FPGA chip for the various dynamic range requirements.


Computation ◽  
2021 ◽  
Vol 9 (2) ◽  
pp. 9
Author(s):  
Konstantin Isupov

Residue number system (RNS) is known for its parallel arithmetic and has been used in recent decades in various important applications, from digital signal processing and deep neural networks to cryptography and high-precision computation. However, comparison, sign identification, overflow detection, and division are still hard to implement in RNS. For such operations, most of the methods proposed in the literature only support small dynamic ranges (up to several tens of bits), so they are only suitable for low-precision applications. We recently proposed a method that supports arbitrary moduli sets with cryptographically sized dynamic ranges, up to several thousands of bits. The practical interest of our method compared to existing methods is that it relies only on very fast standard floating-point operations, so it is suitable for multiple-precision applications and can be efficiently implemented on many general-purpose platforms that support IEEE 754 arithmetic. In this paper, we make further improvements to this method and demonstrate that it can successfully be applied to implement efficient data-parallel primitives operating in the RNS domain, namely finding the maximum element of an array of RNS numbers on graphics processing units. Our experimental results on an NVIDIA RTX 2080 GPU show that for random residues and a 128-moduli set with 2048-bit dynamic range, the proposed implementation reduces the running time by a factor of 39 and the memory consumption by a factor of 13 compared to an implementation based on mixed-radix conversion.


2014 ◽  
Vol 11 (3) ◽  
pp. 365-377
Author(s):  
Negovan Stamenkovic ◽  
Dragana Zivaljevic ◽  
Vidosav Stojanovic

Implementation of IIR filters in residue number system (RNS) architecture is more complex in comparison to FIR filters, due to introduction of the scaling function. This function performs operation of division by a constant factor, which is usually the power of two, and after that the operation of rounding. In that way dynamic range reduction in digital systems is achieved. There are different methods for scaling operation implementation, already presented in references. In this paper, some RNS dynamic reduction techniques have been analyzed and then application of one selected technique has been presented on example. In all RNS calculations the power of two moduli set {2n-1, 2n, 2n+1} has been applied.


2020 ◽  
Author(s):  
Mohammad Hizzani

Public-Key Cryptosystems are prone to wide range of cryptanalyses due to its property of having key pairs one of them is public. Therefore, the recommended length of these keys is extremely large (e.g. in RSA and D-H the key is at least 2048 bits long) and this leads the computation of such cryptosystems to be slower than the secret-key cryptosystems (i.e. AES and AES-family). Since, the key operation in such systems is the modular multiplication; in this research a novel design for the modular multiplication based on the Montgomery Multiplication, the Residue Number Systems for moduli of any form, and the Signed-Digit Representation is proposed. The proposed design outperforms the current designs in the literature in terms of delay with at least 28% faster for the key of 2048 bits long. Up to our knowledge, this design is the first design that utilizes Signed-Digit Representation with the Residue Number System for moduli of any form.


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