scholarly journals High Precision Multiplier for RNS {2n−1,2n,2n+1}

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1113
Author(s):  
Shang Ma ◽  
Shuai Hu ◽  
Zeguo Yang ◽  
Xuesi Wang ◽  
Meiqing Liu ◽  
...  
Keyword(s):  
High Precision ◽  
Dynamic Range ◽  
Signal To Noise Ratio ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
Extra Effort ◽  
Scale Down ◽  
Weighted Number ◽  
Dsp Systems

The Residue Number System (RNS) is a non-weighted number system. Benefiting from its inherent parallelism, RNS has been widely studied and used in Digital Signal Processing (DSP) systems and cryptography. However, since the dynamic range in RNS has been fixed by its moduli set, it is hard to solve the overflow problem, which can be easily solved in Two’s Complement System (TCS) by expanding the bit-width of it. For the multiplication in RNS, the traditional way to deal with overflow is to scale down the inputs so that the result can fall in its dynamic range. However, it leads to a loss of precision. In this paper, we propose a high-precision RNS multiplier for three-moduli set 2n−1,2n,2n+1, which is the most used moduli set. The proposed multiplier effectively improves the calculation precision by adding several compensatory items to the result. The compensatory items can be obtained directly from preceding scalers with little extra effort. To the best of our knowledge, we are the first one to propose a high-precision RNS multiplier for the moduli set 2n−1,2n,2n+1. Simulation results show that the proposed RNS multiplier can get almost the same calculation precision as the TCS multiplier with respect to Mean Square Error (MSE) and Signal-to-Noise Ratio(SNR), which outperforms the basic scaling RNS multiplier about 2.6–3 times with respect to SNR.

scholarly journals Binary to RNS encoder for the moduli set {2n-1, 2n, 2n+1} with embedded diminished-1 channel for DSP application

2016 ◽  
Vol 29 (1) ◽  
pp. 101-112
Author(s):  
Ivan Krstic ◽  
Negovan Stamenkovic ◽  
Vidosav Stojanovic
Keyword(s):  
Dynamic Range ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
The Other ◽  
Minimal Amount ◽  
Residue Number ◽  
Fpga Chip ◽  
The One ◽  
Xilinx Fpga

A binary-to-residues encoder (forward encoder) is an essential building block for the residue number system digital signal processing (RNS DSP) and as such it should be built with a minimal amount of hardware and be efficient in terms of speed and power. The main parts of the forward encoder are residue generators which are usually classified into two categories: the one based on arbitrary moduli-set which make use of look-up tables, and the other based on the special moduli sets. A new memory less architecture of binary-to-RNS encoder based on the special moduli set {2n?1,2n,2n+1} with embedded modulo 2n+1 channel in the diminished-1 representation is presented. Any of two channels (standard modulo 2n +1, or modulo 2n+1 in the diminished-1 representation) operation can be performed by using a single switch. The proposed encoder has been implemented on a Xilinx FPGA chip for the various dynamic range requirements.

scholarly journals A Fault Tolerant Scheme for Detecting Overflow in Residue Number Microprocessors

2018 ◽  
Vol 7 (02) ◽  
pp. 23578-23587
Author(s):  
Agbedemnab P. A. ◽  
Agebure M. A. ◽  
Akobre S.
Keyword(s):  
Dynamic Range ◽  
Fault Tolerant ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
General Purpose ◽  
Correction Scheme ◽  
Residue Number ◽  
Efficient Scheme ◽  
General Purpose Computer

The decomposition of larger numbers into smaller ones termed as residues is the main operation behind the concept of Residue Number System (RNS); it possesses inherent features such as parallelism and independent digit arithmetic computations. These features of the RNS has made it desirable for applications that require intensive computations such as Digital Signal Processing (DSP), Digital Filtering and Convolutions. Overflow detection is one of the major challenges that confront the efficient implementation of RNS in general purpose computer processors. Overflow occurs in RNS when an illegitimate value is represented within legitimate range – Dynamic Range (DR) as if it is legitimate value. This misrepresentation of results, which usually arises during addition operations ultimately affects systems built on this Number System. It is therefore imperative that steps are taken not to only detect but correct the occurrence of overflow whenever it occurs. In this paper, an additive overflow detection and correction scheme for the moduli set  is presented. The scheme uses a redundant modulus to extend the DR of the moduli set. The proposed scheme is demonstrated theoretically to be an efficient scheme by comparing it to previous similar works.

LARGE DYNAMIC RANGE RNS SYSTEMS AND THEIR RESIDUE TO BINARY CONVERTERS

2007 ◽  
Vol 16 (02) ◽  
pp. 267-286 ◽  
Author(s):  
ALEXANDER SKAVANTZOS ◽  
MOHAMMAD ABDALLAH ◽  
THANOS STOURAITIS
Keyword(s):  
High Speed ◽  
Dynamic Range ◽  
Chinese Remainder Theorem ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
New Class ◽  
Mixed Radix Conversion ◽  
Residue Number ◽  
Signal Processors

The Residue Number System (RNS) is an integer system appropriate for implementing fast digital signal processors. It can be used for supporting high-speed arithmetic by operating in parallel channels without need for exchanging information among the channels. In this paper, two novel RNS are proposed. First, a new RNS system based on the modulus set {2n+1, 2n - 1, 2n + 1, 2n + 2(n+1)/2 + 1, 2n - 2(n+1)/2 + 1}, n odd, is developed, along with an efficient implementation of its residue-to-weighted converter. The new RNS is a balanced five-modulus system, appropriate for large dynamic ranges. The proposed residue-to-binary converter is fast and hardware efficient and is based on a one's complement multi-operand adder that adds operands of size only 80% of the size dictated by the system's dynamic range. Second, a new class of multi-modulus RNS systems is proposed. These systems are based on sets consisting of two groups of moduli with the modulus product within one group being of the form 2a(2b - 1), while the modulus product within the other group is of the form 2c - 1. Their RNS-to-weighted converters are based on efficient combinations of the Chinese Remainder Theorem and Mixed Radix Conversion decoding techniques. Systems based on four, five, and seven moduli are constructed and analyzed. The new systems allow efficient implementations for their RNS-to-weighted decoders, imply fast and balanced RNS arithmetic, and may achieve large dynamic ranges. The presented residue-to-weighted converters for these systems rely on simple mod (2x - 1) hardware, which can be easily implemented as one's complement hardware.

RESIDUE-WEIGHTED NUMBER CONVERSION FOR MODULI SET {2n-1, 2n + 1, 22n + 1, 2n} USING SIGNED-DIGIT NUMBER

2013 ◽  
Vol 22 (01) ◽  
pp. 1250070
Author(s):  
CHANGJUN JIANG ◽  
SHUGANG WEI
Keyword(s):  
Dynamic Range ◽  
Number System ◽  
Residue Number System ◽  
Digit Number ◽  
Number Systems ◽  
Binary Arithmetic ◽  
Array Technology ◽  
Free Constant ◽  
Weighted Number ◽  
Binary Tree Structure

Signed-digit number systems support carry-free, constant time addition. By introducing the signed-digit number arithmetic into a residue number system (RNS), arithmetic operations can be performed efficiently. In this paper, a new algorithm for residue-to-binary conversion for four moduli set {2n-1, 2n + 1, 22n + 1, 2n} that only requires modulo 24n - 1 SD number addition is proposed. This moduli set has 5n-bit dynamic range. Based on the proposed algorithm, the converters are designed with a two-level binary tree structure formed by the modulo 24n - 1 SD number residue adders. Moreover, we simplify the residue adders in converters to obtain more area and time efficiency. The comparison of the converters proposed with the converter using binary arithmetic using 0.18 μm CMOS gate array technology yields reductions in delays of 44%, 60% and 75% for n = 4, n = 8 and n = 16, respectively.

A High-Performance Signal Processing System for Monopulse Tracking Radar

2011 ◽  
Vol 383-390 ◽  
pp. 471-475
Author(s):  
Yong Bin Hong ◽  
Cheng Fa Xu ◽  
Mei Guo Gao ◽  
Li Zhi Zhao
Keyword(s):  
Signal Processing ◽  
High Performance ◽  
Dynamic Range ◽  
Signal To Noise Ratio ◽  
Processing System ◽  
Digital Signal ◽  
Radar Signal ◽  
Signal Processing System ◽  
Parallel Pipelined ◽  
Tracking Radar

A radar signal processing system characterizing high instantaneous dynamic range and low system latency is designed based on a specifically developed signal processing platform. Instantaneous dynamic range loss is a critical problem when digital signal processing is performed on fixed-point FPGAs. In this paper, the problem is well resolved by increasing the wordlength according to signal-to-noise ratio (SNR) gain of the algorithms through the data path. The distinctive software structure featuring parallel pipelined processing and “data flow drive” reduces the system latency to one coherent processing interval (CPI), which significantly improves the maximum tracking angular velocity of the monopulse tracking radar. Additionally, some important electronic counter-countermeasures (ECCM) are incorporated into this signal processing system.

scholarly journals Image multiplexing using residue number system coding over MIMO-OFDM communication system

2019 ◽  
Vol 9 (6) ◽  
pp. 4815
Author(s):  
Mohamed Ibrahim Youssif ◽  
Amr ElSayed Emam ◽  
Mohamed Abd ElGhany
Keyword(s):  
Image Quality ◽  
Communication System ◽  
Signal To Noise Ratio ◽  
Image Transmission ◽  
Number System ◽  
Residue Number System ◽  
Signal To Noise ◽  
Residue Number ◽  
Mimo Ofdm ◽  
Noise Ratio

<p>Image transmission over Orthogonal Frequency-Division Multiplexing (OFDM) communication system is prone to distortion and noise due to the encountered High-Peak-to-Average-Power-Ratio (PAPR) generated from the OFDM block. This paper studies the utilization of Residue Number System (RNS) as a coding scheme for digital image transmission over Multiple-Input-Multiple-Output (MIMO) – OFDM transceiver communication system. The use of the independent parallel feature of RNS, as well as the reduced signal amplitude to convert the input signal to parallel smaller residue signals, enable to reduce the signal PAPR, decreasing the signal distortion and the Bit Error Rate (BER). Consequently, improving the received Signal-to-Noise Ratio (SNR) and enhancing the received image quality. The performance analyzed though BER, and PAPR. Moreover, image quality measurement is achieved through evaluating the Mean Squared Error (MSE), Peak Signal to Noise Ratio (PSNR), and the correlation values between the initial and retrieved images. Simulation results had shown the performance of transmission/reception model with and without RNS coding implementation.</p><p> </p>

scholarly journals NULL Convention Floating Point Multiplier

2015 ◽  
Vol 2015 ◽  
pp. 1-10 ◽  
Author(s):  
Anitha Juliette Albert ◽  
Seshasayanan Ramachandran
Keyword(s):  
High Precision ◽  
Dynamic Range ◽  
Digital Signal ◽  
High Dynamic Range ◽  
Floating Point ◽  
Single Precision ◽  
Critical Part ◽  
Point Multiplication ◽  
Null Convention Logic ◽  
High Dynamic

Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The novelty of the research is that it is the first ever NULL convention logic multiplier, designed to perform floating point multiplication. The proposed multiplier offers substantial decrease in power consumption when compared with its synchronous version. Performance attributes of the NULL convention logic floating point multiplier, obtained from Xilinx simulation and Cadence, are compared with its equivalent synchronous implementation.

Perspective and Opportunities of Modulo 2n−1 Multipliers in Residue Number System: A Review

2020 ◽  
Vol 29 (11) ◽  
pp. 2030008
Author(s):  
Raj Kumar ◽  
Ritesh Kumar Jaiswal ◽  
Ram Awadh Mishra
Keyword(s):  
Word Length ◽  
Dynamic Range ◽  
High Dynamic Range ◽  
Number System ◽  
Residue Number System ◽  
System A ◽  
Essential Components ◽  
Residue Number ◽  
Speed Up ◽  
Computational Circuits

Modulo multiplier has been attracting considerable attention as one of the essential components of residue number system (RNS)-based computational circuits. This paper contributes a comprehensive review in the design of modulo [Formula: see text] multipliers for the first time. The modulo multipliers can be implemented using ROM (look-up-table) as well as VLSI components (memoryless); however, the former is preferable for lower word-length and later for larger word-length. The modular and parallelism properties of RNS are used to improve the performance of memoryless multipliers. Moreover, a Booth-encoding algorithm is used to speed-up the multipliers. Also, an advanced modulo [Formula: see text] multiplier based on redundant RNS (RRNS) could be further chosen for very high dynamic range. These perspectives of modulo [Formula: see text] multipliers have been extensively studied for recent state-of-the-art and analyzed using Synopsis design compiler tool.

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