Design of a Bio-Inspired Embryonic Cellular Array Based on Bus Structure

2019 ◽  
Vol 29 (06) ◽  
pp. 2050099
Author(s):  
Tao Wang ◽  
Jinyan Cai ◽  
Yafeng Meng ◽  
Meng Lv ◽  
Zexi Li
Keyword(s):  
Large Scale ◽  
Evaluation Model ◽  
Functional Differentiation ◽  
Digital Circuit ◽  
Resource Consumption ◽  
Internal Communication ◽  
Oxide Semiconductor ◽  
Cellular Array ◽  
Hardware Resource ◽  
Bus Structure

There are some shortcomings, such as huge hardware resource consumption, functional differentiation is difficult and limited fault detection coverage, when embryonic cellular array (ECA) is used to design large-scale circuit. In this paper, the structure characteristics and communication method of multicellular organism are analyzed briefly, and a new bio-inspired ECA based on bus structure (BECA) is proposed, besides that the corresponding self-repairing strategy is designed. First, the functional decomposition has been applied in BECA, which uses bus structure to realize internal communication. BECA consists of bus and electronic tissues (ET), which can be used to realize large-scale circuit. C17 circuit in ISCAS85 circuit library is chosen as experiment subject, and experiment simulation results indicate that BECA based on bus structure is suitable for large-scale circuit, and the faults occurred in ET can be repaired effectively. In order to research BECA from the mathematical point of view, the reliability evaluation model of BECA is established, which is based on [Formula: see text]-out-of-[Formula: see text] system reliability model. In addition, the hardware resource consumption model of BECA is established by analyzing the number of metal oxide semiconductor (MOS) transistors that ECA consumed. Based on BECA reliability and hardware resource consumption evaluation model, comparative experiment is studied, and the results indicate that the proposed ECA can improve the reliability of circuit and reduce hardware resource consumption effectively. Therefore, the BECA presented will play an important role in designing large-scale digital circuit with self-repairing ability.

Intelligent Lighting Control System in Large-Scale Sports Competition Venues

2018 ◽  
pp. 172-182 ◽  
Author(s):  
Shengmin CAO
Keyword(s):  
Control System ◽  
Large Scale ◽  
Comprehensive Evaluation ◽  
Evaluation Model ◽  
Fuzzy Comprehensive Evaluation ◽  
Practical Significance ◽  
Lighting Control ◽  
Sports Events ◽  
Planning And Design ◽  
Comprehensive Evaluation Model

This paper mainly studies the application of intelligent lighting control system in different sports events in large sports competition venues. We take the Xiantao Stadium, a large­scale sports competition venue in Zaozhuang City, Shandong Province as an example, to study its intelligent lighting control system. In this paper, the PID (proportion – integral – derivative) incremental control model and the Karatsuba multiplication model are used, and the intelligent lighting control system is designed and implemented by multi­level fuzzy comprehensive evaluation model. Finally, the paper evaluates the actual effect of the intelligent lighting control system. The research shows that the intelligent lighting control system designed in this paper can accurately control the lighting of different sports in large stadiums. The research in this paper has important practical significance for the planning and design of large­scale sports competition venues.

scholarly journals A low-area high-efficiency video coding inverse transform core using resource and time sharing architecture

2020 ◽  
Vol 2020 (1) ◽  
Author(s):  
Yuan-Ho Chen ◽  
Chieh-Yang Liu
Keyword(s):  
Video Coding ◽  
Large Scale ◽  
High Efficiency ◽  
Vlsi Design ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Time Sharing ◽  
High Efficiency Video Coding ◽  
Low Area ◽  
Matrix Products

AbstractIn this paper, a very-large-scale integration (VLSI) design that can support high-efficiency video coding inverse discrete cosine transform (IDCT) for multiple transform sizes is proposed. The proposed two-dimensional (2-D) IDCT is implemented at a low area by using a single one-dimensional (1-D) IDCT core with a transpose memory. The proposed 1-D IDCT core decomposes a 32-point transform into 16-, 8-, and 4-point matrix products according to the symmetric property of the transform coefficient. Moreover, we use the shift-and-add unit to share hardware resources between multiple transform dimension matrix products. The 1-D IDCT core can simultaneously calculate the first- and second-dimensional data. The results indicate that the proposed 2-D IDCT core has a throughput rate of 250 MP/s, with only 110 K gate counts when implemented into the Taiwan semiconductor manufacturing (TSMC) 90-nm complementary metal-oxide-semiconductor (CMOS) technology. The results show the proposed circuit has the smallest area supporting the multiple transform sizes.

scholarly journals Automated Visual Recognizability Evaluation of Traffic Sign Based on 3D LiDAR Point Clouds

2019 ◽  
Vol 11 (12) ◽  
pp. 1453 ◽  
Author(s):  
Shanxin Zhang ◽  
Cheng Wang ◽  
Lili Lin ◽  
Chenglu Wen ◽  
Chenhui Yang ◽  
...  
Keyword(s):  
Traffic Safety ◽  
Laser Scanning ◽  
Large Scale ◽  
Evaluation Method ◽  
Evaluation Model ◽  
Point Clouds ◽  
Traffic Sign ◽  
Traffic Signs ◽  
3D Point Clouds ◽  
Traffic Environment

Maintaining the high visual recognizability of traffic signs for traffic safety is a key matter for road network management. Mobile Laser Scanning (MLS) systems provide efficient way of 3D measurement over large-scale traffic environment. This paper presents a quantitative visual recognizability evaluation method for traffic signs in large-scale traffic environment based on traffic recognition theory and MLS 3D point clouds. We first propose the Visibility Evaluation Model (VEM) to quantitatively describe the visibility of traffic sign from any given viewpoint, then we proposed the concept of visual recognizability field and Traffic Sign Visual Recognizability Evaluation Model (TSVREM) to measure the visual recognizability of a traffic sign. Finally, we present an automatic TSVREM calculation algorithm for MLS 3D point clouds. Experimental results on real MLS 3D point clouds show that the proposed method is feasible and efficient.

A large scale cellular array processor

1985 ◽  
Author(s):  
Toshio Kondo ◽  
Tayoshi Nakashima ◽  
Toshio Tsuchiya ◽  
Yoshi Sugiyama ◽  
Tsuneta Sudo
Keyword(s):  
Large Scale ◽  
Array Processor ◽  
Cellular Array

scholarly journals Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit

2021 ◽  
Vol 12 (3) ◽  
pp. 3037-3045
Author(s):  
M. Naga Gowtham Et.al
Keyword(s):  
High Speed ◽  
Supply Voltage ◽  
Average Power ◽  
Full Adder ◽  
Digital Circuit ◽  
Oxide Semiconductor ◽  
Transmission Gate ◽  
Average Power Consumption ◽  
Pass Transistor ◽  
Pass Transistor Logic

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

scholarly journals Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit

2021 ◽  
Vol 12 (5) ◽  
pp. 92-100
Author(s):  
M. Naga Gowtham, P.S Hari Krishna Reddy, K Jeevitha, K Hari Kishore, E Raghuveera, Shaik Razia
Keyword(s):  
High Speed ◽  
Supply Voltage ◽  
Average Power ◽  
Full Adder ◽  
Digital Circuit ◽  
Oxide Semiconductor ◽  
Transmission Gate ◽  
Average Power Consumption ◽  
Pass Transistor ◽  
Pass Transistor Logic

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

scholarly journals Process Design Kit and Design Automation for Flexible Hybrid Electronics

2019 ◽  
Vol 16 (3) ◽  
pp. 117-123
Author(s):  
Tsung-Ching Huang ◽  
Ting Lei ◽  
Leilai Shao ◽  
Sridhar Sivapurapu ◽  
Madhavan Swaminathan ◽  
...  
Keyword(s):  
Process Design ◽  
Design Automation ◽  
High Performance ◽  
Large Scale ◽  
Low Cost ◽  
Thin Film Transistor ◽  
Solution Process ◽  
Oxide Semiconductor ◽  
Wearable Electronics ◽  
Wide Range

Abstract High-performance low-cost flexible hybrid electronics (FHE) are desirable for applications such as internet of things and wearable electronics. Carbon nanotube (CNT) thin-film transistor (TFT) is a promising candidate for high-performance FHE because of its high carrier mobility, superior mechanical flexibility, and material compatibility with low-cost printing and solution processes. Flexible sensors and peripheral CNT-TFT circuits, such as decoders, drivers, and sense amplifiers, can be printed and hybrid-integrated with thinned (<50 μm) silicon chips on soft, thin, and flexible substrates for a wide range of applications, from flexible displays to wearable medical devices. Here, we report (1) a process design kit (PDK) to enable FHE design automation for large-scale FHE circuits and (2) solution process-proven intellectual property blocks for TFT circuits design, including Pseudo-Complementary Metal-Oxide-Semiconductor (Pseudo-CMOS) flexible digital logic and analog amplifiers. The FHE-PDK is fully compatible with popular silicon design tools for design and simulation of hybrid-integrated flexible circuits.

scholarly journals Cooperation between HNF-1α, Cdx2, and GATA-4 in initiating an enterocytic differentiation program in a normal human intestinal epithelial progenitor cell line

2010 ◽  
Vol 298 (4) ◽  
pp. G504-G517 ◽  
Author(s):  
Yannick D. Benoit ◽  
Fréderic Paré ◽  
Caroline Francoeur ◽  
Dominique Jean ◽  
Eric Tremblay ◽  
...  
Keyword(s):  
Transcription Factors ◽  
Cell Line ◽  
Large Scale ◽  
Morphological Changes ◽  
Ectopic Expression ◽  
Functional Differentiation ◽  
Stem Cell Markers ◽  
Intestinal Epithelial ◽  
Differentiation Markers ◽  
Functional Features

In the intestinal epithelium, the Cdx, GATA, and HNF transcription factor families are responsible for the expression of differentiation markers such as sucrase-isomaltase. Although previous studies have shown that Cdx2 can induce differentiation in rat intestinal IEC-6 cells, no data are available concerning the direct implication of transcription factors on differentiation in human normal intestinal epithelial cell types. We investigated the role of Cdx2, GATA-4, and HNF-1α using the undifferentiated human intestinal epithelial crypt cell line HIEC. These transcription factors were tested on proliferation and expression of polarization and differentiation markers. Ectopic expression of Cdx2 or HNF-1α, alone or in combination, altered cell proliferation abilities through the regulation of cyclin D1 and p27 expression. HNF-1α and GATA-4 together induced morphological modifications of the cells toward polarization, resulting in the appearance of functional features such as microvilli. HNF-1α was also sufficient to induce the expression of cadherins and dipeptidylpeptidase, whereas in combination with Cdx2 it allowed the expression of the late differentiation marker sucrase-isomaltase. Large-scale analysis of gene expression confirmed the cooperative effect of these factors. Finally, although DcamKL1 and Musashi-1 expression were downregulated in differentiated HIEC, other intestinal stem cell markers, such as Bmi1, were unaffected. These observations show that, in cooperation with Cdx2, HNF-1α acts as a key factor on human intestinal cells to trigger the onset of their functional differentiation program whereas GATA-4 appears to promote morphological changes.

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