scholarly journals Silicon Nanowires: A Breakthrough for Thermoelectric Applications

Materials ◽  
2021 ◽  
Vol 14 (18) ◽  
pp. 5305
Author(s):  
Giovanni Pennelli ◽  
Elisabetta Dimaggio ◽  
Antonella Masci
Keyword(s):  
Integrated Circuits ◽  
Power Factor ◽  
Silicon Nanowires ◽  
Silicon Nanowire ◽  
Large Temperature ◽  
Nanowire Diameter ◽  
Large Numbers ◽  
High Power Factor ◽  
Experimental Works ◽  
Very High

The potentialities of silicon as a starting material for electronic devices are well known and largely exploited, driving the worldwide spreading of integrated circuits. When nanostructured, silicon is also an excellent material for thermoelectric applications, and hence it could give a significant contribution in the fundamental fields of energy micro-harvesting (scavenging) and macro-harvesting. On the basis of recently published experimental works, we show that the power factor of silicon is very high in a large temperature range (from room temperature up to 900 K). Combining the high power factor with the reduced thermal conductivity of monocrystalline silicon nanowires and nanostructures, we show that the foreseen figure of merit ZT could be very high, reaching values well above 1 at temperatures around 900 K. We report the best parameters to optimize the thermoelectric properties of silicon nanostructures, in terms of doping concentration and nanowire diameter. At the end, we report some technological processes and solutions for the fabrication of macroscopic thermoelectric devices, based on large numbers of silicon nanowire/nanostructures, showing some fabricated demonstrators.

scholarly journals Current transport and thermoelectric properties of very high power factor Fe3O4/SiO2/p-type Si(001) devices

2014 ◽  
Vol 115 (3) ◽  
pp. 033709 ◽  
Author(s):  
M. Zervos ◽  
Z. Viskadourakis ◽  
G. Athanasopoulos ◽  
R. Flores ◽  
O. Conde ◽  
...  
Keyword(s):  
Thermoelectric Properties ◽  
Power Factor ◽  
High Power ◽  
Current Transport ◽  
High Power Factor ◽  
P Type ◽  
Very High

SILICON NANOWIRES FORMATION IN CMOS COMPATIBLE MANNER

2006 ◽  
Vol 05 (04n05) ◽  
pp. 445-451 ◽  
Author(s):  
AJAY AGARWAL ◽  
N. BALASUBRAMANIAN ◽  
N. RANGANATHAN ◽  
R. KUMAR
Keyword(s):  
Silicon Nanowires ◽  
Silicon Nanowire ◽  
Electrical Characterization ◽  
Single Electron Transistor ◽  
Bulk Silicon ◽  
Nanowire Diameter ◽  
Section Shape ◽  
Medical Sensors ◽  
Cmos Compatible

We present CMOS compatible fabrication technique for silicon nanowire ( SiNW ) on bulk silicon wafers. Our method uses saw-tooth etch-profiles of fins followed by self-limiting oxidation to form vertically self-aligned horizontal SiNW down to 5 nm diameter. The concept of modifying the cross-section shape of SiNW from triangular to circular and the ability to achieve desired nanowire diameter are unique in this work. Nanowires formed by such technique can be utilized to realize several nanoelectronics devices like gate-all-around transistor, single-electron-transistor, etc.; NEMS and bio-medical sensors; all in a CMOS friendly manner. The physical and electrical characterization of the SiNW is also presented in this paper.

scholarly journals The Electronic Properties of Silicon Nanowires during Their Dissolution under Simulated Physiological Conditions

2019 ◽  
Vol 9 (4) ◽  
pp. 804
Author(s):  
Annina Steinbach ◽  
Tanja Sandner ◽  
Madeleine Nilsen ◽  
Ximeng Hua ◽  
Ragul Sivakumar ◽  
...  
Keyword(s):  
Band Structure ◽  
Fermi Level ◽  
Electronic Properties ◽  
Silicon Nanowires ◽  
Silicon Nanowire ◽  
Conduction Band Edge ◽  
Surface Band ◽  
Nanowire Diameter ◽  
Biomedical Sensors ◽  
Physiological Conditions

Silicon nanowires are considered promising future biomedical sensors. However, their limited stability under physiological conditions poses a challenge in sensor development and necessitates a significantly improved knowledge of underlying effects as well as new solutions to enhance silicon nanowire durability. In the present study, we deduced the dissolution rates of silicon nanowires under simulated physiological conditions from atomic force microscopy measurements. We correlated the relevant change in nanowire diameter to changes in the electronic properties by examining the I-V characteristics of kinked silicon nanowire p–n junctions. Contact potential difference measurements and ambient pressure photoemission spectroscopy additionally gave insights into the electronic surface band structure. During the first week of immersion, the Fermi level of n-type silicon nanowires shifted considerably to higher energies, partly even above the conduction band edge, which manifested in an increased conductivity. After about a week, the Fermi level stabilized and the conductivity decreased consistently with the decreasing diameter caused by continuous nanowire dissolution. Our results show that a physiological environment can substantially affect the surface band structure of silicon nanowire devices, and with it, their electronic properties. Therefore, it is necessary to study these effects and find strategies to gain reliable biomedical sensors.

A Systematic Study of Metal-assisted Chemical Etching Parameters for Well-Ordered Silicon Nanowire Array Fabrication

2012 ◽  
Vol 1408 ◽  
Author(s):  
Arif S. Alagoz ◽  
Tansel Karabacak
Keyword(s):  
Silicon Nanowires ◽  
Chemical Etching ◽  
Crystalline Silicon ◽  
Silicon Nanowire ◽  
Etching Rate ◽  
Nanowire Array ◽  
Lithium Ion ◽  
Nanowire Diameter ◽  
Silicon Nanowire Array ◽  
Metal Assisted Chemical Etching

ABSTRACTMetal-assisted chemical etching is a simple and low-cost silicon nanowire fabrication method which allows control of nanowire diameter, length, shape and orientation. In this work, we fabricated well-ordered silicon nanowire array by patterning gold thin film by nanosphere lithography and etching single crystalline silicon wafer by metal-assisted chemical etching technique. We investigated relation between etched solution concentration and nanowire morphology, wafer crystal orientation, etching rate. This well-ordered silicon nanowires arrays have the potential applications in many fields but especially next generation energy related applications from solar cells to lithium-ion batteries.

scholarly journals Seebeck coefficient of silicon nanowire forests doped by thermal diffusion

2020 ◽  
Vol 11 ◽  
pp. 1707-1713
Author(s):  
Shaimaa Elyamny ◽  
Elisabetta Dimaggio ◽  
Giovanni Pennelli
Keyword(s):  
Seebeck Coefficient ◽  
Thermal Diffusion ◽  
Silicon Nanowires ◽  
High Efficiency ◽  
Silicon Nanowire ◽  
Electrical Energy ◽  
Etching Technique ◽  
High Power Factor ◽  
Static Conditions ◽  
Good Agreement

Thermoelectric generators made by large arrays of nanowires perpendicular to a silicon substrate, that is, so-called silicon nanowire forests are fabricated on large areas by an inexpensive metal-assisted etching technique. After fabrication, a thermal diffusion process is used for doping the nanowire forest with phosphorous. A suitable experimental technique has been developed for the measurement of the Seebeck coefficient under static conditions, and results are reported for different doping parameters. These results are in good agreement with numerical simulations of the doping process applied to silicon nanowires. These devices, based on doped nanowire forests, offer a possible route for the exploitation of the high power factor of silicon, which, combined with the very low thermal conductivity of nanostructures, will yield a high efficiency of the conversion of thermal to electrical energy.

Structural changes in silicon-on-insulator material during post-implantation annealing

1986 ◽  
Vol 44 ◽  
pp. 736-737
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
High Speed ◽  
Structural Changes ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Quality ◽  
Radiation Hardened ◽  
Post Implantation ◽  
Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

High Power Factor Based Novel Design of Sodium Lamps

2010 ◽  
Vol 4 (2) ◽  
pp. 1-6
Author(s):  
S. Sankar ◽  
◽  
G. Gokula Krishnan ◽  
Keyword(s):  
Power Factor ◽  
High Power ◽  
High Power Factor ◽  
Novel Design
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