Spin-Based Fully Nonvolatile Full-Adder Circuit for Computing in Memory

SPIN ◽  
2019 ◽  
Vol 09 (01) ◽  
pp. 1950007 ◽  
Author(s):  
Abdolah Amirany ◽  
Ramin Rajaei
Keyword(s):  
High Performance ◽  
Soft Errors ◽  
Magnetic Tunnel Junction ◽  
High Volume ◽  
Full Adder ◽  
Cmos Technology ◽  
Logic Circuits ◽  
Volume Data ◽  
Single Node ◽  
Radiation Induced

As CMOS technology scales down toward below 2-digit nanometer dimensions, exponentially increasing leakage power, vulnerability to radiation induced soft errors have become a major problem in today’s logic circuits. Emerging spin-based logic circuits and architectures based on nonvolatile magnetic tunnel junction (MTJ) cells show a great potential to overcome the aforementioned issues. However, radiation induced soft errors are still a problem in MTJ-based circuits as they need sequential peripheral CMOS circuits for sensing the MTJs. This paper proposes a novel nonvolatile and low-cost radiation hardened magnetic full adder (MFA). In comparison with the previous designs, the proposed MFA is capable of tolerating particle strikes regardless of the amount of charge induced to a single node and even multiple nodes. Besides, the proposed MFA offers low power operation, low area and high performance as compared with previous counterparts. One of the most important features suggested by the proposed MFA circuit is full nonvolatility. Nonvolatile logic circuits remove the cost of high volume data transactions between memory and logic and also facilitate power gating in logic-in-memory architectures.

scholarly journals High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

2021 ◽  
pp. 263-269
Author(s):  
Tejaswini M. L ◽  
Aishwarya H ◽  
Akhila M ◽  
B. G. Manasa
Keyword(s):  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Cmos Technology ◽  
Power Performance ◽  
High Speed Design ◽  
Power Delay Product ◽  
Full Swing ◽  
Output Swing ◽  
High Output

The main aim of our work is to achieve low power, high speed design goals. The proposed hybrid adder is designed to meet the requirements of high output swing and minimum power. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of XOR-XNOR circuit. In hybrid FAs maximum power is consumed by XOR-XNOR circuit. In this paper 10T XOR-XNOR is proposed, which provide good driving capabilities and full swing output simultaneously without using any external inverter. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. This circuit outperforms its counterparts showing power delay product is reduced than that of available XOR-XNOR modules. Four different full adder designs are proposed utilizing 10T XOR-XNOR, sum and carry modules. The proposed FAs provide improvement in terms of PDP than that of other architectures. To evaluate the performance of proposed full adder circuit, we embedded it in a 4-bit and 8-bit cascaded full adder. Among all FAs two of the proposed FAs provide the best performance for a higher number of bits.

A Low-Cost Highly Reliable Spintronic True Random Number Generator Circuit for Secure Cryptography

SPIN ◽  
2019 ◽  
Vol 10 (01) ◽  
pp. 2050003 ◽  
Author(s):  
Iman Alibeigi ◽  
Abdolah Amirany ◽  
Ramin Rajaei ◽  
Mahmoud Tabandeh ◽  
Saeed Bagheri Shouraki
Keyword(s):  
High Speed ◽  
High Performance ◽  
Random Number ◽  
Low Cost ◽  
Random Number Generator ◽  
Magnetic Tunnel Junction ◽  
Random Number Generation ◽  
Cmos Technology ◽  
Random Numbers ◽  
Number Generation

Generation of random numbers is one of the most important steps in cryptographic algorithms. High endurance, high performance and low energy consumption are the attractive features offered by the Magnetic Tunnel Junction (MTJ) devices. Therefore, they have been considered as one of the promising candidates for next-generation digital integrated circuits. In this paper, a new circuit design for true random number generation using MTJs is proposed. Our proposed circuit offers a high speed, low power and a truly random number generation. In our design, we employed two MTJs that are configured in special states. Generated random bit at the output of the proposed circuit is returned to the write circuit to be written in the relevant cell for the next random generation. In a random bitstream, all bits must have the same chance of being “0”or “1”. We have proposed a new XOR-based method in this paper to resolve this issue in multiple random generators that produce truly random numbers with a different number of ones and zeros in the output stream. The simulation results using a 45[Formula: see text]nm CMOS technology with a special model of MTJ validated the advantages offered by the proposed circuit.

DESIGN AND ANALYSIS OF A NOVEL LOW PDP FULL ADDER CELL

2011 ◽  
Vol 20 (03) ◽  
pp. 439-445 ◽  
Author(s):  
M. H. GHADIRY ◽  
ABU KHARI A'AIN ◽  
M. NADI S.
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Performance ◽  
Full Adder ◽  
Cmos Technology ◽  
Accurate Analysis ◽  
And Performance ◽  
Full Swing ◽  
Driving Capability

This paper, presents a new full-swing low power high performance full adder circuit in CMOS technology. It benefits from a full swing XOR-XNOR module with no feedback transistors, which decreases delay and power consumption. In addition, high driving capability of COUT module and low PDP design of SUM module contribute to more PDP reduction in cascaded mode. In order to have accurate analysis, the new circuit along with several well-known full adders from literature have been modeled and compared with CADENCE. Comparison consists of power consumption, performance, PDP, and area. Results show that there are improvements in both power consumption and performance. This design trades area with low PDP.

Low Power High Performance Full Adder Design Using Gate Diffusion Input Techniques

2020 ◽  
Vol 17 (4) ◽  
pp. 1595-1599
Author(s):  
N. Suresh ◽  
K. Subba Rao ◽  
R. Vassoudevan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Large Scale ◽  
Digital Signal ◽  
Full Adder ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Essential Components

Very Large Scale Integrated (VLSI) technology for a widespread use of high performance portable integrated circuit (IC) devices such as MP3, PDA, mobile phones is increasing rapidly. Most of the VLSI applications, such as digital signal processing, image processing and microprocessors, extensively use arithmetic operations. In this research novel low power full adder architecture has been proposed for various applications which uses the advanced adder and multiplier designs. A full-adder is one of the essential components in digital circuit design; many improvements have been made to reduce the architecture of a full adder. In this research modified full adder using GDI technique is proposed to achieve low power consumption. By using GDI cell, the transistor count is greatly reduced, thereby reducing the power consumption and propagation delay while maintaining the low complexity of the logic design. The parameters in terms of Power, Delay, and Surface area are investigated by comparison of the proposed GDI technology with an optimized 90 nm CMOS technology.

scholarly journals Broadening access to supercomputers for CMIP6 and CORDEX multimodel comparisons

2020 ◽  
Author(s):  
Stephan Kindermann ◽  
Maria Moreno
Keyword(s):  
High Performance ◽  
Data Science ◽  
High Volume ◽  
System Modelling ◽  
Earth System ◽  
Volume Data ◽  
Server Side ◽  
Network Bandwidth ◽  
Data Collections ◽  
Client Side

<p>We will present a new service designed to assist the users of model data in running their analyses in world-class supercomputers. The increase of data volumes and model complexities can be challenging for data users with limited access to high performance computers or low network bandwidth. To avoid heavy data transfers, strong memory requirements, and slow sequential processing, the data science community is rapidly moving from classical client-side to new server-side frameworks. Three simple steps enable server-side users to compute in parallel and near the data: (1) discover the data you are interested in, (2) perform your analyses and visualizations in the supercomputer, and (3) download the outcome. A server-side service is especially beneficial for exploiting the high-volume data collections produced in the framework of internationally coordinated model intercomparison projects like CMIP5/6 and CORDEX and disseminated via the  Earth System Grid Federation (ESGF) infrastructure. To facilitate the adoption of server-side capabilities by the ESGF users, the infrastructure project of the European Network for Earth System Modelling (IS-ENES3) is now opening its high performance resources and data pools at the CMCC (Italy), JASMIN (UK), IPSL (France), and DKRZ (Germany) supercomputing centers. The data pools allow access to results from several models on the same site and the data and resources are locally maintained by the hosts. Besides, our server-side framework not only speeds the workload but also reduces the errors in file format conversions and standardizations and software dependencies and upgrade. The service is founded by the EU Commission and it is free of charge. Find more information here: https://portal.enes.org/data/data-metadata-service/analysis-platforms. Demos and tutorials have been created by a dedicated user support team. We will present several use cases showing how easy and flexible it is to use our analysis platforms for multimodel comparisons of CMIP5/6 and CORDEX data. </p>

A Review of QCA Nanotechnology as an Alternate to CMOS

2021 ◽  
Vol 17 ◽  
Author(s):  
Syed Farah Naz ◽  
Sadat Riyaz ◽  
Vijay Kumar Sharma
Keyword(s):  
Metal Oxide ◽  
Complementary Metal Oxide Semiconductor ◽  
Full Adder ◽  
Cmos Technology ◽  
Logic Circuits ◽  
Extensive Study ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Data Movement ◽  
Mos Device

Background: The human ken and understanding about esoteric phenomenon develops the period from space to the sub-atomic level. The passion to further explore the unexplored domains and dimensions boosts the human advancement in a cyclic way. A significant part of such passion follows in the electronics industry. Moore’s law is reaching the practical limitations because of further scaling of metal oxide semiconductor (MOS) devices. The need of a more dexterous and effective technology approach is demanded. Quantum-dot cellular automata (QCA) is an emerging technology which avoids the physical limitations of the MOS device. QCA is a dynamic computational transistor paradigm that addresses device density, power, operating frequency and interconnection problems. It requires an extensive study to know the fundamentals of logic implementation. Objective: Immense research and experiments due same vigor led to the evolving nanotechnology and a feasible alternative to complementary metal oxide semiconductor (CMOS) technology. A comprehensive study is presented in the paper to enhance the basics of QCA technology and the way of implementation of the logic circuits. Different existing circuits using QCA technology are discussed and compared for different parameters. Methods: Scaling the devices can reduce the power consumption of the MOS device. Quantum dots are nanostructures made from semi-conductive conventional materials. It is possible to model these constructions as 3-dimensional (3D) quantum energy wells. Logical operations and data movement are performed using Columbic interaction between nearby QCA cells instead of current flow. Results: The focus of this review paper is to study the trends which have been proposed and compared the designs for various digital circuits. The performance of different circuits such as XOR, adder, reversible gates and flip-flops are provided. Different logic circuits are compared on the parameters such as cell count, area and latency. At least 10 QCA cells are used for the XOR gate with 1 clock latency. Minimum 44 QCA cells are required to make a full adder with 1.25 clock latency.

scholarly journals Design and Analysis of a New Carbon Nanotube Full Adder Cell

2011 ◽  
Vol 2011 ◽  
pp. 1-6 ◽  
Author(s):  
M. H. Ghadiry ◽  
Asrulnizam Abd Manaf ◽  
M. T. Ahmadi ◽  
Hatef Sadeghi ◽  
M. Nadi Senejani
Keyword(s):  
Carbon Nanotube ◽  
High Performance ◽  
Full Adder ◽  
Cmos Technology ◽  
Ultra Low Power ◽  
And Performance ◽  
Carbon Nanotube Technology ◽  
Power Delay Product ◽  
Full Swing ◽  
Very High

A novel full adder circuit is presented. The main aim is to reduce power delay product (PDP) in the presented full adder cell. A new method is used in order to design a full-swing full adder cell with low number of transistors. The proposed full adder is implemented in MOSFET-like carbon nanotube technology and the layout is provided based on standard 32 nm technology from MOSIS. The simulation results using HSPICE show that there are substantial improvements in both power and performance of the proposed circuit compared to the latest designs. In addition, the proposed circuit has been implemented in conventional 32 nm process to compare the benefits of using MOSFET-like carbon nanotubes in arithmetic circuits over conventional CMOS technology. The proposed circuit can be applied in very high performance and ultra-low-power applications.

scholarly journals Skip high-volume data transfer and access free computing resources for your CMIP6 multi-model analyses

2021 ◽  
Author(s):  
Maria Moreno de Castro ◽  
Marco Kulüke ◽  
Fabian Wachsmann ◽  
Regina Kwee-Hinzmann ◽  
Stephan Kindermann ◽  
...  
Keyword(s):  
High Performance ◽  
Process Model ◽  
Impact Analysis ◽  
Data Transfer ◽  
Computing Time ◽  
High Volume ◽  
System Modelling ◽  
Earth System ◽  
Volume Data ◽  
Climate Data

<p>Tired of downloading tons of model results? Is your internet connection flakey? Are you about to overload your computer’s memory with the constant increase of data volume and you need more computing resources? You can request free of charge computing time at one of the supercomputers of the Infrastructure of the European Network of Earth System modelling (IS-ENES)<sup>1</sup>, the European part of Earth System Grid Federation (ESGF)<sup>2</sup>, which also hosts and maintains more than 6 Petabytes of CMIP6 and CORDEX data.</p><p>Thanks to this new EU Comission funded service, you can run your own scripts in your favorite programming language and straightforward pre- and post-process model data. There is no need for heavy data transfer, just load with one line of code the data slice you need because your script will directly access the data pool. Therefore, days-lasting calculations will be done in seconds. You can test the service, we very easily provide pre-access activities.</p><p>In this session we will run Jupyter notebooks directly on the German Climate Computing Center (DKRZ)<sup>3</sup>, one of the ENES high performance computers and a ESGF data center, showing how to load, filter, concatenate, take means, and plot several CMIP6 models to compare their results, use some CMIP6 models to calculate some climate indexes for any location and period, and evaluate model skills with observational data. We will use Climate Data Operators (cdo)<sup>4</sup> and Python packages for Big Data manipulation, as Intake<sup>5</sup>, to easily extract the data from the huge catalog, and Xarray<sup>6</sup>, to easily read NetDCF files and scale to parallel computing. We are continuously creating more use cases for multi-model evaluation, mechanisms of variability, and impact analysis, visit the demos, find more information, and apply here: https://portal.enes.org/data/data-metadata-service/analysis-platforms.<br><br>[1] https://is.enes.org/<br>[2] https://esgf.llnl.gov/<br>[3] https://www.dkrz.de/<br>[4] https://code.mpimet.mpg.de/projects/cdo/<br>[5] https://intake.readthedocs.io/en/latest/<br>[6] http://xarray.pydata.org/en/stable/</p>

scholarly journals DESIGN OF ENERGY EFFICIENT HYBRID 1-BIT FULL ADDER FOR ARITHMETIC APPLICATIONS

2020 ◽  
Vol 4 (6) ◽  
pp. 15-18
Author(s):  
Haroon Rasheed S ◽  
Mohan Das S ◽  
Samba Sivudu Gaddam
Keyword(s):  
Energy Consumption ◽  
Energy Efficient ◽  
High Performance ◽  
Low Voltage ◽  
Supply Voltage ◽  
Full Adder ◽  
Cmos Technology ◽  
Internal Logic ◽  
Logic Cells ◽  
Power Delay Product

This paper presents an energy efficient 1-bit full adder designed with a low voltage and high performance internal logic cells which leads to have abridged Power Delay Product (PDP). The customized XNOR and XOR gates, a necessary entity, are also presented. The simulations for the designed circuits performed in cadence virtuoso tool with 45-nm CMOS technology at a supply voltage of 0.9 Volts. The proposed 1-bit adder cell is compared with various trendy adders based on speed, power consumption and energy (PDP). The proposed adder schemes with modified internal entity cells achieve significant savings in terms of delay and energy consumption and which are more than 77% and 40.47% respectively when compared with conventional “C-CMOS” 1-bit full adder and other counter parts.

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