A Quality-assured Approximate Hardware Accelerators–based on Machine Learning and Dynamic Partial Reconfiguration

2021 ◽  
Vol 17 (4) ◽  
pp. 1-19
Author(s):  
Mahmoud Masadeh ◽  
Yassmeen Elderhalli ◽  
Osman Hasan ◽  
Sofiene Tahar
Keyword(s):  
Machine Learning ◽  
Power Consumption ◽  
Error Resilience ◽  
User Preferences ◽  
Machine Learning Algorithms ◽  
Approximate Computing ◽  
Partial Reconfiguration ◽  
Efficient Design ◽  
Fpga Design ◽  
Dynamic Partial Reconfiguration

Machine learning is widely used these days to extract meaningful information out of the Zettabytes of sensors data collected daily. All applications require analyzing and understanding the data to identify trends, e.g., surveillance, exhibit some error tolerance. Approximate computing has emerged as an energy-efficient design paradigm aiming to take advantage of the intrinsic error resilience in a wide set of error-tolerant applications. Thus, inexact results could reduce power consumption, delay, area, and execution time. To increase the energy-efficiency of machine learning on FPGA, we consider approximation at the hardware level, e.g., approximate multipliers. However, errors in approximate computing heavily depend on the application, the applied inputs, and user preferences. However, dynamic partial reconfiguration has been introduced, as a key differentiating capability in recent FPGAs, to significantly reduce design area, power consumption, and reconfiguration time by adaptively changing a selective part of the FPGA design without interrupting the remaining system. Thus, integrating “Dynamic Partial Reconfiguration” (DPR) with “Approximate Computing” (AC) will significantly ameliorate the efficiency of FPGA-based design approximation. In this article, we propose hardware-efficient quality-controlled approximate accelerators, which are suitable to be implemented in FPGA-based machine learning algorithms as well as any error-resilient applications. Experimental results using three case studies of image blending, audio blending, and image filtering applications demonstrate that the proposed adaptive approximate accelerator satisfies the required quality with an accuracy of 81.82%, 80.4%, and 89.4%, respectively. On average, the partial bitstream was found to be 28.6 smaller than the full bitstream .

Dynamic partial reconfiguration enchanced with security system for reduced area and low power consumption

2020 ◽  
Vol 76 ◽  
pp. 103088
Author(s):  
R. Saravana Ram ◽  
M. Lordwin Cecil Prabhaker ◽  
K. Suresh ◽  
Kamalraj Subramaniam ◽  
M. Venkatesan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Security System ◽  
Low Power Consumption ◽  
Partial Reconfiguration ◽  
Dynamic Partial Reconfiguration

scholarly journals Algorithmic-Level Approximate Tensorial SVM Using High-Level Synthesis on FPGA

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 205
Author(s):  
Hamoud Younes ◽  
Ali Ibrahim ◽  
Mostafa Rizk ◽  
Maurizio Valle
Keyword(s):  
Machine Learning ◽  
State Of The Art ◽  
Machine Learning Algorithms ◽  
High Level Synthesis ◽  
Support Vector ◽  
Svm Classifier ◽  
Approximate Computing ◽  
Classification Framework ◽  
Time Latency ◽  
High Level

Approximate Computing Techniques (ACT) are promising solutions towards the achievement of reduced energy, time latency and hardware size for embedded implementations of machine learning algorithms. In this paper, we present the first FPGA implementation of an approximate tensorial Support Vector Machine (SVM) classifier with algorithmic level ACTs using High-Level Synthesis (HLS). A touch modality classification framework was adopted to validate the effectiveness of the proposed implementation. When compared to exact implementation presented in the state-of-the-art, the proposed implementation achieves a reduction in power consumption by up to 49% with a speedup of 3.2×. Moreover, the hardware resources are reduced by 40% while consuming 82% less energy in classifying an input touch with an accuracy loss less than 5%.

scholarly journals Gutter oil detection for food safety based on multi-feature machine learning and implementation on FPGA with approximate multipliers

2021 ◽  
Vol 7 ◽  
pp. e774
Author(s):  
Wei Jiang ◽  
Yuhanxiao Ma ◽  
Ruiqi Chen
Keyword(s):  
Machine Learning ◽  
Food Safety ◽  
Power Consumption ◽  
Field Tests ◽  
Significant Loss ◽  
Machine Learning Algorithms ◽  
Comprehensive Method ◽  
Multiple Feature ◽  
Actual Use ◽  
First Time

Since consuming gutter oil does great harm to people’s health, the Food Safety Administration has always been seeking for a more effective and timely supervision. As laboratory tests consume much time, and existing field tests have excessive limitations, a more comprehensive method is in great need. This is the first time a study proposes machine learning algorithms for real-time gutter oil detection under multiple feature dimensions. Moreover, it is deployed on FPGA to be low-power and portable for actual use. Firstly, a variety of oil samples are generated by simulating the real detection environment. Next, based on previous studies, sensors are used to collect significant features that help distinguish gutter oil. Then, the acquired features are filtered and compared using a variety of classifiers. The best classification result is obtained by k-NN with an accuracy of 97.18%, and the algorithm is deployed to FPGA with no significant loss of accuracy. Power consumption is further reduced with the approximate multiplier we designed. Finally, the experimental results show that compared with all other platforms, the whole FPGA-based classification process consumes 4.77 µs and the power consumption is 65.62 mW. The dataset, source code and the 3D modeling file are all open-sourced.

scholarly journals Energy Profile Prediction of Milling Processes Using Machine Learning Techniques

2020 ◽  
pp. 1-11
Author(s):  
Matthias Mühlbauer ◽  
Hubert Würschinger ◽  
Dominik Polzer ◽  
Nico Hanenkamp
Keyword(s):  
Machine Learning ◽  
Power Consumption ◽  
Model Building ◽  
Milling Process ◽  
Machine Learning Algorithms ◽  
Machine Learning Techniques ◽  
Learning Techniques ◽  
Accurate Forecast ◽  
The Individual ◽  
Cutting Processes

AbstractThe prediction of the power consumption increases the transparency and the understanding of a cutting process, this delivers various potentials. Beside the planning and optimization of manufacturing processes, there are application areas in different kinds of deviation detection and condition monitoring. Due to the complicated stochastic processes during the cutting processes, analytical approaches quickly reach their limits. Since the 1980s, approaches for predicting the time or energy consumption use empirical models. Nevertheless, most of the existing models regard only static snapshots and are not able to picture the dynamic load fluctuations during the entire milling process. This paper describes a data-driven way for a more detailed prediction of the power consumption for a milling process using Machine Learning techniques. To increase the accuracy we used separate models and machine learning algorithms for different operations of the milling machine to predict the required time and energy. The merger of the individual models allows finally the accurate forecast of the load profile of the milling process for a specific machine tool. The following method introduces the whole pipeline from the data acquisition, over the preprocessing and the model building to the validation.

scholarly journals Sustainable Modular Adaptive Redundancy Technique Emphasizing Partial Reconfiguration for Reduced Power Consumption

2011 ◽  
Vol 2011 ◽  
pp. 1-25 ◽  
Author(s):  
R. Al-Haddad ◽  
R. Oreifej ◽  
R. A. Ashraf ◽  
R. F. DeMara
Keyword(s):  
Power Consumption ◽  
Fault Tolerant ◽  
Repair Time ◽  
Self Healing ◽  
Partial Reconfiguration ◽  
Organic System ◽  
Dynamic Partial Reconfiguration ◽  
Novel Approach ◽  
Field Programmable ◽  
Sobel Edge Detection

As reconfigurable devices' capacities and the complexity of applications that use them increase, the need forself-relianceof deployed systems becomes increasingly prominent. Organic computing paradigms have been proposed for fault-tolerant systems because they promote behaviors that allow complex digital systems to adapt and survive in demanding environments. In this paper, we develop asustainable modular adaptive redundancy technique (SMART)composed of a two-layered organic system. The hardware layer is implemented on a XilinxVirtex-4Field Programmable Gate Array (FPGA) to provide self-repair using a novel approach calledreconfigurable adaptive redundancy system (RARS). The software layer supervises the organic activities on the FPGA and extends the self-healing capabilities through application-independent, intrinsic, and evolutionary repair techniques that leverage the benefits of dynamic partial reconfiguration (PR). SMART was evaluated using a Sobel edge-detection application and was shown to tolerate stressful sequences of injected transient and permanent faults while reducing dynamic power consumption by 30% compared to conventionaltriple modular redundancy (TMR)techniques, with nominal impact on the fault-tolerance capabilities. Moreover, PR is employed to keep the system on line while under repair and also to reduce repair time. Experiments have shown a 27.48% decrease in repair time when PR is employed compared to the full bitstream configuration case.

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