Effect of Hydrogen on p-Type Epitaxial Silicon Sheet-Resistance Measurements

1999 ◽  
Vol 1 (2) ◽  
pp. 100 ◽  
Author(s):  
T. I. Kamins
1995 ◽  
Vol 386 ◽  
Author(s):  
John Lowell ◽  
Valerie Wenner ◽  
Damon Debusk

ABSTRACTIn CMOS, the use of epitaxial layers for prevention of latch-up in logic technologies is well-known and pervasive. One of the crucial parameters is the amount of metallic contamination due to transition metals such as Fe in the epi since this phenomena effects both device performance and quality. However, the ability to measure this parameter on product material is not generally available due to inherent problems with most known methods. The limitation of traditional surface photovoltage is that the deep optical penetration of over a hundred microns is well-beyond the depth of most epitaxial layers and does not accurately profile the epitaxial region [1]. In this paper we report on the application of optical surface photovoltage (SPV) using a set of ultra-shallow optical filters to both quantify and qualify as-grown epitaxial layers on CZ P-type silicon. We believe that a non-contact, SPV measurement of Fe concentration and diffusion lengths within an epitaxial region has not been previously reported.


2010 ◽  
Vol 24 (30) ◽  
pp. 5867-5875
Author(s):  
JICHENG ZHOU ◽  
ZHENG LIU ◽  
XUQIANG ZHENG ◽  
YOUZHEN LI ◽  
DITIAN LUO

Ta–Si–N thin films and Cu/Ta–Si–N thin films were deposited on p-type Si (111) substrates by magnetron reactive sputtering. Then the films were characterized by four-point probe sheet resistance measurement, atomic force microscopy, X-ray diffraction method and scanning electron microscope, respectively. The experimental results show that the sheet resistance of Ta–Si–N thin film increases with N content. And the surface roughness of the thin film first decreases and then increases with N content. By increasing the N content, the diffusion barrier property of Ta–Si–N thin film can be improved; however, this improvement is not evident when N content beyond 56%. The as-deposited Ta–Si thin film is nano-crystalline. When doped with N, the as-deposited thin film becomes amorphous. The crystallization of Ta–Si–N thin film occurs again at high temperature. Cu atoms diffuse through grain boundaries of Ta–Si–N thin film into Si , and this leads to failure of the diffusion barrier.


1986 ◽  
Vol 71 ◽  
Author(s):  
Walter H. Johnson ◽  
W. Andrew Keenan ◽  
Alan K. Smith

AbstractSheet resistance mapping has become an indispensable tool in characterizing ion implanters for both integrated circuit manufacturers and equipment manufacturers. The sheet resistance mapping technique is now being extended into additional applications such as the characterization of metal deposition, CVD, and epitaxial silicon growth. This technique has become especially necessary with the advent of 150mm and 200mm wafers, where 5 or 9 site measurements cannot provide sufficient data essential for process control.In order to optimize the performance of an epi reactor it is necessary to control and characterize the gas flows and temperature distributions inside the reactor. The control of these variables is essential for thickness and resistivity uniformity in epi layers. This paper describes the use of sheet resistance profiles and contour maps to study the resistivity and thickness uniformity variations in an epi reactor. The sheet resistance maps allow for control of the epi process without requiring data from other test sources.This ensures real time process control for production, as well as very rapid feedback for maintenance while doing equipment repair.


2000 ◽  
Vol 5 (S1) ◽  
pp. 845-851
Author(s):  
G. Dang ◽  
X. A. Cao ◽  
F. Ren ◽  
S. J. Pearton ◽  
J. Han ◽  
...  

Different ions (Ti+, O+, Fe+, Cr+) were implanted at multiple energies into GaN field effect transistor structures (n and p-type). The implantation was found to create deep states with energy levels in the range EC −0.20 to 0.49 eV in n-GaN and at EV +0.44 eV in p-GaN after annealing at 450-650 °C. The sheet resistance of the GaN was at a maximum after annealing at these temperatures, reaching values of ∼4×1012 Ω/□ in n-GaN and ∼1010 Ω/□ in p-GaN. The mechanism for the implant isolation was damage-related trap formation for all of the ions investigated, and there was no evidence of chemically induced isolation.


1999 ◽  
Vol 564 ◽  
Author(s):  
K. Das ◽  
S. A. Alterovitz

AbstractA Cu-based metallization scheme has been studied for establishing low resistance contacts for a Si/SiGe/Si heterojunction bipolar transistor (HBT) structure. As-grown doped layers were further implanted with BF2 and As ions for the p-type base and n-type emitter layers, respectively, in order to produce a low sheet resistance surface layer. Contacts were metallized using an e-beam deposited multilayer structure of Ti/Cu/Ti/Al. Specific contact resistances of the order of 10−7 Ω cm2 or lower were obtained.


1987 ◽  
Vol 93 ◽  
Author(s):  
D. R. Myers ◽  
H. J. Stein ◽  
S. S. Tsao ◽  
G. W. Arnold ◽  
R. C. Hughes ◽  
...  

ABSTRACTWe have examined the microstructure and the transport properties of nitrogen-implanted silicon-on-insulator wafers, as well as the performance of integrated-circuit transistors fabricated in this material. The insulating regions were fabricated in silicon by the unpatterned implantation of 4×1017 /cm2, 300 keV nitrogen dimers followed by annealing at 1473 K for 5 hours. For these parameters, the buried nitrogen-implanted layer crystallized into α-silicon nitride, and contains ≈20% excess silicon in the form of silicon inclusions of 5–15 nm diameter. The surface silicon layers are characterized by low-mobility, p-type conduction. The buried dielectric has a resistivity of approximately 108 Ωcm. Functional p-channel, integrated circuit transistors have been fabricated in n-type epitaxial silicon grown over the buried-nitride wafers. These transistors devices are similar in performance to those fabricated in bulk silicon,(hole mobilities in inversion layers of 140 cm2/V-s), and demonstrate the suitability of the buried nitride process for integrated circuit applications.


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