Characterization of Buried-Nitride Silicon for Integrated Circuit Applications

1987 ◽  
Vol 93 ◽  
Author(s):  
D. R. Myers ◽  
H. J. Stein ◽  
S. S. Tsao ◽  
G. W. Arnold ◽  
R. C. Hughes ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Transport Properties ◽  
Integrated Circuit ◽  
Silicon On Insulator ◽  
Epitaxial Silicon ◽  
Bulk Silicon ◽  
Excess Silicon ◽  
P Type ◽  
Type Conduction

ABSTRACTWe have examined the microstructure and the transport properties of nitrogen-implanted silicon-on-insulator wafers, as well as the performance of integrated-circuit transistors fabricated in this material. The insulating regions were fabricated in silicon by the unpatterned implantation of 4×1017 /cm2, 300 keV nitrogen dimers followed by annealing at 1473 K for 5 hours. For these parameters, the buried nitrogen-implanted layer crystallized into α-silicon nitride, and contains ≈20% excess silicon in the form of silicon inclusions of 5–15 nm diameter. The surface silicon layers are characterized by low-mobility, p-type conduction. The buried dielectric has a resistivity of approximately 108 Ωcm. Functional p-channel, integrated circuit transistors have been fabricated in n-type epitaxial silicon grown over the buried-nitride wafers. These transistors devices are similar in performance to those fabricated in bulk silicon,(hole mobilities in inversion layers of 140 cm2/V-s), and demonstrate the suitability of the buried nitride process for integrated circuit applications.

Effect of B dose and Ge preamorphization energy on the electrical and structural properties of ultrashallow junctions in silicon-on-insulator

2006 ◽  
Vol 912 ◽  
Author(s):  
Justin J Hamilton ◽  
Erik JH Collart ◽  
Benjamin Colombeau ◽  
Massimo Bersani ◽  
Damiano Giubertoni ◽  
...  
Keyword(s):  
Structural Properties ◽  
Solid Phase ◽  
Silicon Film ◽  
Silicon On Insulator ◽  
Bulk Silicon ◽  
Defect Band ◽  
Future Technology ◽  
Ultrashallow Junctions ◽  
P Type ◽  
Technology Nodes

AbstractFormation of highly activated, ultra-shallow and abrupt profiles is a key requirement for the next generations of CMOS devices, particularly for source-drain extensions. For p-type dopant implants (boron), a promising method of increasing junction abruptness is to use Ge preamorphizing implants prior to ultra-low energy B implantation and solid-phase epitaxy regrowth to re-crystallize the amorphous Si. However, for future technology nodes, new issues arise when bulk silicon is supplanted by silicon-on-insulator (SOI). Previous results have shown that the buried Si/SiO2 interface can improve dopant activation, but the effect depends on the detailed preamorphization conditions and further optimization is required. In this paper a range of B doses and Ge energies have been chosen in order to situate the end-of-range (EOR) defect band at various distances from the back interface of the active silicon film (the interface with the buried oxide), in order to explore and optimize further the effect of the interface on dopant behavior. Electrical and structural properties were measured by Hall Effect and SIMS techniques. The results show that the boron deactivates less in SOI material than in bulk silicon, and crucially, that the effect increases as the distance from the EOR defect band to the back interface is decreased. For the closest distances, an increase in junction steepness is also observed, even though the B is located close to the top surface, and thus far from the back interface. The position of the EOR defect band shows the strongest influence for lower B doses.

Wafer Characterization of an Epi Reactor Using Sheet Resistance Mapping

1986 ◽  
Vol 71 ◽  
Author(s):  
Walter H. Johnson ◽  
W. Andrew Keenan ◽  
Alan K. Smith
Keyword(s):  
Process Control ◽  
Sheet Resistance ◽  
Integrated Circuit ◽  
Mapping Technique ◽  
Gas Flows ◽  
Epitaxial Silicon ◽  
Contour Maps ◽  
Silicon Growth ◽  
Indispensable Tool

AbstractSheet resistance mapping has become an indispensable tool in characterizing ion implanters for both integrated circuit manufacturers and equipment manufacturers. The sheet resistance mapping technique is now being extended into additional applications such as the characterization of metal deposition, CVD, and epitaxial silicon growth. This technique has become especially necessary with the advent of 150mm and 200mm wafers, where 5 or 9 site measurements cannot provide sufficient data essential for process control.In order to optimize the performance of an epi reactor it is necessary to control and characterize the gas flows and temperature distributions inside the reactor. The control of these variables is essential for thickness and resistivity uniformity in epi layers. This paper describes the use of sheet resistance profiles and contour maps to study the resistivity and thickness uniformity variations in an epi reactor. The sheet resistance maps allow for control of the epi process without requiring data from other test sources.This ensures real time process control for production, as well as very rapid feedback for maintenance while doing equipment repair.

P-type Doping of SIC by Aluminum Implantation for Advanced Device Applications

1995 ◽  
Vol 410 ◽  
Author(s):  
Maria A. Caleca ◽  
Honghua Du ◽  
Joseph R. Flemish ◽  
Stephen P. Withrow
Keyword(s):  
Dopant Concentration ◽  
Dopant Activation ◽  
Force Microscopy ◽  
Atomic Force ◽  
Aluminum Implantation ◽  
Device Applications ◽  
P Type ◽  
Type Conduction ◽  
Annealing Method

ABSTRACT6H-SiC epitaxial layers with a background n-type dopant concentration of 1 × 1016/cm3 were hot implanted to doses ranging from 4.0 × 1013 to 1.8 × 1014 Al ions/cm2 at 65, 135, and 220 keV to achieve a box-type implant distribution to a depth of 300 nm. Electrical activation of dopants was carried out using a proximity annealing method at 1500°C in a buffer environment to retard surface degradation of the SiC samples. Measurements using atomic force microscopy illustrated the morphological stability of the SiC surface during the high-temperature annealing. Transmission line measurements showed some degree of dopant activation. Characterization of fabricated p-n junction diodes demonstrated p-type conduction in the aluminum-implanted SiC samples.

Effect of Dopant on N-Type Bi2Te2.7Se0.3 Thermoelectric Materials Fabricated by Spark Plasma Sintering

2008 ◽  
Vol 368-372 ◽  
pp. 544-546
Author(s):  
Dong Choul Cho ◽  
Jae Seol Lee ◽  
Chul Ho Lim ◽  
Chi Hwan Lee
Keyword(s):  
Thermal Conductivity ◽  
Spark Plasma Sintering ◽  
Sintering Temperature ◽  
Sintered Sample ◽  
Dopant Content ◽  
Plasma Sintering ◽  
Spark Plasma ◽  
P Type ◽  
Type Conduction

The n-type Bi2Te2.7Se0.3 compounds were fabricated to investigate the characterization of spark plasma sintering with various SbI3 dopant contents. The Bi2Te2.7Se0.3 compounds with SbI3 dopant content is exhibited n-type conduction characterization, but the Bi2Te2.7Se0.3 compounds without SbI3 dopant content is exhibited p-type conduction characterization. The maximum Seebeck coeficient represented with 0.05wt.% SbI3 dopant content. The Seebeck coefficient of the sintered sample with increasing sintering temperature is increased from -158 to -182 μV/K. The electrical resistivity and thermal conductivity with 0.05wt.% SbI3 dopant content were 1.0 m and 1.33 W/mK, respectively.

scholarly journals X-ray characterization of BUSARD chip: A HV-SOI monolithic particle detector with pixel sensors under the buried oxide

2021 ◽  
Vol 16 (12) ◽  
pp. P12030
Author(s):  
F. Alcalde Bessia ◽  
J. Lipovetzky ◽  
I. Perić
Keyword(s):  
Integrated Circuit ◽  
Pulse Height ◽  
Digital Processing ◽  
Silicon On Insulator ◽  
Energy Calibration ◽  
X Ray ◽  
Buried Oxide ◽  
Pixel Sensors ◽  
A Charge

Abstract This work presents the design of BUSARD, an application specific integrated circuit (ASIC) for the detection of ionizing particles. The ASIC is a monolithic active pixel sensor which has been fabricated in a High-Voltage Silicon-On-Insulator (HV-SOI) process that allows the fabrication of a buried N+ diffusion below the Buried OXide (BOX) as a standard processing step. The first version of the chip, BUSARD-A, takes advantage of this buried diffusion as an ionizing particle sensor. It includes a small array of 13×13 pixels, with a pitch of 80 μm, and each pixel has one buried diffusion with a charge amplifier, discriminator with offset tuning and digital processing. The detector has several operation modes including particle counting and Time-over-Threshold (ToT). An initial X-ray characterization of the detector was carried out, obtaining several pulse height and ToT spectra, which then were used to perform the energy calibration of the device. The Molybdenum 𝐊α emission was measured with a standard deviation of 127 e- of ENC by using the analog pulse output, and with 276 e- of ENC by using the ToT digital output. The resolution in ToT mode is dominated by the pixel-to-pixel variation.

Characterization of Si/CaF2/Si Epitaxial Films Grown By MBE

1985 ◽  
Vol 43 ◽  
pp. 362-363
Author(s):  
N. Lewis ◽  
E. L. Hall ◽  
R. W. Fathauer ◽  
L. Schowalter
Keyword(s):  
Integrated Circuit ◽  
Room Temperature ◽  
Molecular Beam ◽  
Lattice Mismatch ◽  
Research Effort ◽  
Epitaxial Films ◽  
Silicon On Insulator ◽  
3 Dimensional ◽  
Large Research

There has been a large research effort throughout the electronics industry to develop epitaxial Si/insulator/Si structures for silicon-on-insulator (SOI) and 3-dimensional integrated circuit applications. Molecular beam epitaxy (MBE) is one promising method of producing these SOI structures. The use of CaF2 as an insulator is interesting because of the similarities in the Si (diamond cubic) and CaF2, (cubic fluorite) structures, where the lattice mismatch between these two materials is only 0.6% at room temperature. CaF2 also evaporates congruently during epitaxial growth by MBE, therefore, avoiding problems with the control of film stoichiometry. This paper describes the characterization of epitaxial Si overlayer and CaF2, insulator films which were grown on a (111) single crystal Si substrate.

Electron microscopy of defects in silicon-on-insulator structures formed by selective epitaxial growth

1993 ◽  
Vol 51 ◽  
pp. 798-799
Author(s):  
Z. S. H. Weng-Sieh ◽  
J. C. Lou ◽  
W. G. Oldham ◽  
R. Gronsky
Keyword(s):  
Epitaxial Growth ◽  
Integrated Circuit ◽  
Silicon Substrate ◽  
New Technology ◽  
Three Dimensional ◽  
Chemical Vapor ◽  
Nucleation And Growth ◽  
Silicon On Insulator ◽  
Epitaxial Silicon ◽  
Selective Epitaxial Growth

In the interest of obtaining increased integrated circuit device density, a relatively new technology known as selective epitaxial growth (SEG) of silicon is being explored, especially for improved isolation of devices including possible three dimensional (vertical) integration. This technology involves the deposition and selective nucleation and growth of silicon from the vapor phase, seeded by the silicon substrate. The process is “selective” because nucleation and growth occurs on the silicon substrate but is prohibited on the oxide. The epitaxial silicon proceeds to grow upward and laterally over the oxide.Silicon deposition was performed in a horizontal hot-walled low pressure chemical vapor deposition (LPCVD) reactor. A dry thermal oxide was grown on the substrates, patterned, and etched to create seed windows. A 900 °C prebake was performed at a pressure of 6 torr in a hydrogen ambient for a period of 15 minutes, with in some cases, a small concentration (approximately 0.025%) of dichlorosilane (DCS) gas, and deposition was performed at 850 °C through the decomposition of DCS gas: SiH2Cl2 -> Si(s)+ 2HCl(g).

scholarly journals Synthesis and Characterization of CZTS Thin Films by Sol-Gel Method without Sulfurization

2014 ◽  
Vol 2014 ◽  
pp. 1-6 ◽  
Author(s):  
Xiaoqi Yu ◽  
Aobo Ren ◽  
Fogen Wang ◽  
Ci Wang ◽  
Jingquan Zhang ◽  
...  
Keyword(s):  
Energy Gap ◽  
Sol Gel ◽  
Synthesis And Characterization ◽  
Layer By Layer ◽  
Czts Thin Films ◽  
P Type ◽  
Sem Morphology ◽  
Deposited Films ◽  
Type Conduction

One process of layer-by-layer sol-gel deposition without sulfurization was developed. The CZTS films with 1.2 μm and the sulfur ratio of ~48% were prepared and their characteristics were measured. The as-deposited and annealed films are of Kesterite structure. The as-deposited films do not present obvious electric conduction type. However, the annealed 9-LAY-ANN film is p-type conduction and has sheet resistance of 4.08 kΩ/□ and resistivity of 4.896 × 10−1 Ω·cm. The optic energy gap is 1.50 eV for as-deposited films and is 1.46 eV after being annealed. The region deposited by using Lo-Con solution is more compact than that by the Hi-Con solution from SEM morphology images.

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