scholarly journals Model-integrated Tools for the Design of Dynamically Reconfigurable Systems

VLSI Design ◽  
2000 ◽  
Vol 10 (3) ◽  
pp. 281-306 ◽  
Author(s):  
Ted Bapty ◽  
Sandeep Neema ◽  
Jason Scott ◽  
Janos Sztipanovits ◽  
Sameh Asaad
Keyword(s):  
Reconfigurable Computing ◽  
High Performance ◽  
Formal Analysis ◽  
Specific Model ◽  
Design Flow ◽  
Dynamically Reconfigurable ◽  
Domain Specific ◽  
Runtime Environment ◽  
Analysis And Synthesis ◽  
Execution Semantics

Several classes of modern applications demand very high performance from systems with minimal resources. These applications must also be flexible to operate in a rapidly changing environment. Achieving high performance from limited resources demands application-specific architectures, while flexibility requires architectural adaptation capabilities. Reconfigurable computing devices promise to meet both needs. While these devices are currently available, the issue of how to design these systems is unresolved. This paper describes an environment for design capture, analysis and synthesis of dynamically adaptive computing applications. The representation methodology is captured in a Domain-Specific, Model-Integrated Computing framework. Formal analysis tools are integrated into the design flow to analyze the design space to produce a constrained set of solutions. HW/SW Co-simulations verify the function of the system prior to implementation. Finally, a set of hardware and software subsystems are synthesized to implement the multi-modal, dynamically adaptive application. The application executes under a runtime environment, which supports common execution semantics across software and hardware. An application example is presented.

Dynamically Reconfigurable Hardware for Evolving Bio-Inspired Architectures

2010 ◽  
pp. 1-22 ◽  
Author(s):  
Andres Upegui
Keyword(s):  
Reconfigurable Computing ◽  
High Performance ◽  
Environmental Changes ◽  
Boolean Networks ◽  
Research Field ◽  
Evolvable Hardware ◽  
Neuron Models ◽  
Random Boolean Networks ◽  
Dynamically Reconfigurable ◽  
Spiking Neuron Models

During the last few years, reconfigurable computing devices have experienced an impressive development in their resource availability, speed, and configurability. Currently, commercial FPGAs offer the possibility of self-reconfiguring by partially modifying their configuration bit-string, providing high architectural flexibility, while guaranteeing high performance. On the other hand, we have bio-inspired hardware, a large research field taking inspiration from living beings in order to design hardware systems, which includes diverse approaches like evolvable hardware, neural hardware, and fuzzy hardware. Living beings are well known for their high adaptability to environmental changes, featuring very flexible adaptations at several levels. Bio-inspired hardware systems require such flexibility to be provided by the hardware platform on which the system is implemented. Even though some commercial FPGAs provide enhanced reconfigurability features such as partial and dynamic reconfiguration, their utilization is still in the early stages and they are not well supported by FPGA vendors, thus making their inclusion difficult in existing bio-inspired systems. This chapter presents a set of methodologies and architectures for exploiting the reconfigurability advantages of current commercial FPGAs in the design of bio-inspired hardware systems. Among the presented architectures are neural networks, spiking neuron models, fuzzy systems, cellular automata and Random Boolean Networks.

Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme)

2007 ◽  
Vol 49 (3) ◽  
Author(s):  
Heiko Hinkelmann ◽  
Peter Zipf ◽  
Manfred Glesner ◽  
Thilo Pionteck
Keyword(s):  
Wireless Communication ◽  
Reconfigurable Computing ◽  
Energy Efficient ◽  
Communication Systems ◽  
High Performance ◽  
Wireless Communication Systems ◽  
Computing Systems ◽  
Dynamically Reconfigurable ◽  
Hardware Platforms ◽  
Application Specific

In this paper we will demonstrate that dynamically reconfigurable computing is the key technology to enable small and energy-efficient hardware platforms for wireless communication systems, which provide the flexibility needed for keeping up with evolving standards and protocols. Two application-specific dynamically reconfigurable systems for WLANs and wireless sensor networks will be presented. The first architecture clearly shows that highly dynamic reconfiguration approaches can provide flexible and high-performance hardware platforms that are smaller than standard ASIC solutions. The second architecture serves as a case study for the design of energy-efficient dynamically reconfigurable computing systems.

Measurement Invariance of Divergent Thinking Across Gender, Age, and School Forms

2009 ◽  
Vol 25 (1) ◽  
pp. 1-7 ◽  
Author(s):  
Jörg-Tobias Kuhn ◽  
Heinz Holling
Keyword(s):  
Measurement Invariance ◽  
Divergent Thinking ◽  
Factor Model ◽  
Age Groups ◽  
Thinking Skills ◽  
Specific Model ◽  
Confirmatory Factor Analyses ◽  
Domain Specific ◽  
Gender And Age ◽  
Confirmatory Factor

The present study explores the factorial structure and the degree of measurement invariance of 12 divergent thinking tests. In a large sample of German students (N = 1328), a three-factor model representing verbal, figural, and numerical divergent thinking was supported. Multigroup confirmatory factor analyses revealed that partial strong measurement invariance was tenable across gender and age groups as well as school forms. Latent mean comparisons resulted in significantly higher divergent thinking skills for females and students in schools with higher mean IQ. Older students exhibited higher latent means on the verbal and figural factor, but not on the numerical factor. These results suggest that a domain-specific model of divergent thinking may be assumed, although further research is needed to elucidate the sources that negatively affect measurement invariance.

APA Book Talk: The Psychology of High Performance: Developing Human Potential Into Domain-Specific Talent

2020 ◽  
Author(s):  
Jamie Buck ◽  
Rena Subotnik ◽  
Frank Worrell ◽  
Paula Olszewski-Kubilius ◽  
Chi Wang
Keyword(s):  
High Performance ◽  
Human Potential ◽  
Domain Specific ◽  
Book Talk

Design and Layout of a High-Performance PWM Control Class D Amplifiers IC Systems

2012 ◽  
Vol 203 ◽  
pp. 469-473
Author(s):  
Ruei Chang Chen ◽  
Shih Fong Lee
Keyword(s):  
Low Power ◽  
High Performance ◽  
Low Voltage ◽  
Design Flow ◽  
Total Power ◽  
Cmos Process ◽  
Low Power Circuits ◽  
Class D ◽  
Total Power Consumption ◽  
Power Circuits

This paper presents the design and implementation of a novel pulse width modulation control class D amplifiers chip. With high-performance, low-voltage, low-power and small area, these circuits are employed in portable electronic systems, such as the low-power circuits, wireless communication and high-frequency circuit systems. This class D chip followed the chip implementation center advanced design flow, and then was fabricated using Taiwan Semiconductor Manufacture Company 0.35-μm 2P4M mixed-signal CMOS process. The chip supply voltage is 3.3 V which can operate at a maximum frequency of 100 MHz. The total power consumption is 2.8307 mW, and the chip area size is 1.1497×1.1497 mm2. Finally, the class D chip was tested and the experimental results are discussed. From the excellent performance of the chip verified that it can be applied to audio amplifiers, low-power circuits, etc.

Towards A Multi-FPGA Infrared Simulator

2007 ◽  
Vol 4 (4) ◽  
pp. 343-355 ◽  
Author(s):  
Vinay Sriram ◽  
David Kearney
Keyword(s):  
Homeland Security ◽  
Reconfigurable Computing ◽  
High Speed ◽  
High Performance ◽  
Large Scale ◽  
Computation Time ◽  
Ccd Camera ◽  
Hardware Acceleration ◽  
Limiting Factor ◽  
Scene Simulation

High speed infrared (IR) scene simulation is used extensively in defense and homeland security to test sensitivity of IR cameras and accuracy of IR threat detection and tracking algorithms used commonly in IR missile approach warning systems (MAWS). A typical MAWS requires an input scene rate of over 100 scenes/second. Infrared scene simulations typically take 32 minutes to simulate a single IR scene that accounts for effects of atmospheric turbulence, refraction, optical blurring and charge-coupled device (CCD) camera electronic noise on a Pentium 4 (2.8GHz) dual core processor [7]. Thus, in IR scene simulation, the processing power of modern computers is a limiting factor. In this paper we report our research to accelerate IR scene simulation using high performance reconfigurable computing. We constructed a multi Field Programmable Gate Array (FPGA) hardware acceleration platform and accelerated a key computationally intensive IR algorithm over the hardware acceleration platform. We were successful in reducing the computation time of IR scene simulation by over 36%. This research acts as a unique case study for accelerating large scale defense simulations using a high performance multi-FPGA reconfigurable computer.

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