scholarly journals On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays

2008 ◽  
Vol 2008 ◽  
pp. 1-13 ◽  
Author(s):  
Scott Y. L. Chin ◽  
Clarence S. P. Lee ◽  
Steven J. E. Wilton
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
Embedded Memory ◽  
Power Efficient ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Power And Energy ◽  
Embedded Memories ◽  
The Impact

We investigate the power and energy implications of using embedded FPGA memory blocks to implement logic. Previous studies have shown that this technique provides extremely dense implementations of some types of logic circuits, however, these previous studies did not evaluate the impact on power. In this paper, we measure the effects on power and energy as a function of three architectural parameters: the number of available memory blocks, the size of the memory blocks, and the flexibility of the memory blocks. We show that although embedded memories provide area efficient implementations of many circuits, this technique results in additional power consumption. We also show that blocks containing smaller-memory arrays are more power efficient than those containing large arrays, but for most array sizes, the memory blocks should be as flexible as possible. Finally, we show that by combining physical arrays into larger logical memories, and mapping logic in such a way that some physical arrays can be disabled on each access, can reduce the power consumption penalty. The results were obtained from place and routed circuits using standard experimental physical design tools and a detailed power model. Several results were also verified through current measurements on a 0.13 μm CMOS FPGA.

scholarly journals On the Use of Magnetic RAMs in Field-Programmable Gate Arrays

2008 ◽  
Vol 2008 ◽  
pp. 1-9 ◽  
Author(s):  
Y. Guillemenet ◽  
L. Torres ◽  
G. Sassatelli ◽  
N. Bruchon
Keyword(s):  
Power Consumption ◽  
Random Access ◽  
Switching Scheme ◽  
Fpga Design ◽  
Gate Arrays ◽  
Magnetic Switching ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Time Required ◽  
Magnetic Tunneling

This paper describes the integration of field-induced magnetic switching (FIMS) and thermally assisted switching (TAS) magnetic random access memories in FPGA design. The nonvolatility of the latter is achieved through the use of magnetic tunneling junctions (MTJs) in the MRAM cell. A thermally assisted switching scheme helps to reduce power consumption during write operation in comparison to the writing scheme in the FIMS-MTJ device. Moreover, the nonvolatility of such a design based on either an FIMS or a TAS writing scheme should reduce both power consumption and configuration time required at each power up of the circuit in comparison to classical SRAM-based FPGAs. A real-time reconfigurable (RTR) micro-FPGA using FIMS-MRAM or TAS-MRAM allows dynamic reconfiguration mechanisms, while featuring simple design architecture.

scholarly journals Implementation of Leakage Power Reduction Techniques in Field Programmable Device

2019 ◽  
Vol 9 (2) ◽  
pp. 5115-5123
Keyword(s):  
Low Power ◽  
Computer Aided Design ◽  
System Level ◽  
Gate Arrays ◽  
Reduction Techniques ◽  
Field Programmable ◽  
Programmable Device ◽  
Programmable Gate Arrays ◽  
Power And Energy ◽  
Aided Design

This paper provide a summary of low-power technique for field-programmable gate arrays (FPDs). It cover system level propose technique as well as device level propose methods that have besieged present trade devices. In addition to describe present investigate happening circuit level as well as architecture-level create technique. Current studies on power model as well as on low-power computer-aided design (CAD) are also information. At last, it proposes that would allow the use of Field Programmable Device (FPD) equipment in applications where power and energy consumption is critical, such as mobile devices.

scholarly journals Comparison of reconfigurable structures for flexible word-length multiplication

2008 ◽  
Vol 6 ◽  
pp. 113-118 ◽  
Author(s):  
O. A. Pfänder ◽  
R. Nopper ◽  
H.-J. Pfleiderer ◽  
S. Zhou ◽  
A. Bermak
Keyword(s):  
Power Dissipation ◽  
Word Length ◽  
Digital Signal ◽  
Gate Arrays ◽  
Computing Unit ◽  
Field Programmable ◽  
Embedded Blocks ◽  
Programmable Gate Arrays ◽  
Array Structures ◽  
Reconfigurable Structures

Abstract. Binary multiplication continues to be one of the essential arithmetic operations in digital circuits. Even though field-programmable gate arrays (FPGAs) are becoming more and more powerful these days, the vendors cannot avoid implementing multiplications with high word-lengths using embedded blocks instead of configurable logic. But on the other hand, the circuit's efficiency decreases if the provided word-length of the hard-wired multipliers exceeds the precision requirements of the algorithm mapped into the FPGA. Thus it is beneficial to use multiplier blocks with configurable word-length, optimized for area, speed and power dissipation, e.g. regarding digital signal processing (DSP) applications. In this contribution, we present different approaches and structures for the realization of a multiplication with variable precision and perform an objective comparison. This includes one approach based on a modified Baugh and Wooley algorithm and three structures using Booth's arithmetic operand recoding with different array structures. All modules have the option to compute signed two's complement fix-point numbers either as an individual computing unit or interconnected to a superior array. Therefore, a high throughput at low precision through parallelism, or a high precision through concatenation can be achieved.

Design of EMB-Based Moore FSMs

2017 ◽  
Vol 26 (07) ◽  
pp. 1750125 ◽  
Author(s):  
Małgorzata Kołopieńczyk ◽  
Larysa Titarenko ◽  
Alexander Barkalov
Keyword(s):  
Control Unit ◽  
Logic Circuits ◽  
Embedded Memory ◽  
Complexity Of Algorithms ◽  
Gate Arrays ◽  
Control Units ◽  
Finite State ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Effective Use

The complexity of algorithms implemented in digital systems grows. Methods are developed for most effective use of both hardware resources and energy. For engineers the problem of hardware resources optimization in design of control units is still an important issue. The standard way of implementing the control unit as a finite-state machine (FSM) is not satisfactory as it consumes considerable amounts of field-programmable gate arrays (FPGA) resources. This paper is devoted to the design of a Moore FSM in FPGA structure using look-up tables and embedded memory blocks (EMB) elements. The problem background is discussed. The method of the design of Moore FSM logic circuits with EMB based on splitting the set of logical conditions and the encoding of logical conditions is presented. Examples of design and research results are given.

The Impact of Terrestrial Radiation on FPGAs in Data Centers

2022 ◽  
Vol 15 (2) ◽  
pp. 1-21
Author(s):  
Andrew M. Keller ◽  
Michael J. Wirthlin
Keyword(s):  
Data Centers ◽  
Fault Injection ◽  
Computer Networking ◽  
Gate Arrays ◽  
Large Numbers ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Radiation Induced ◽  
Radiation Testing ◽  
The Impact

Field programmable gate arrays (FPGAs) are used in large numbers in data centers around the world. They are used for cloud computing and computer networking. The most common type of FPGA used in data centers are re-programmable SRAM-based FPGAs. These devices offer potential performance and power consumption savings. A single device also carries a small susceptibility to radiation-induced soft errors, which can lead to unexpected behavior. This article examines the impact of terrestrial radiation on FPGAs in data centers. Results from artificial fault injection and accelerated radiation testing on several data-center-like FPGA applications are compared. A new fault injection scheme provides results that are more similar to radiation testing. Silent data corruption (SDC) is the most commonly observed failure mode followed by FPGA unavailable and host unresponsive. A hypothetical deployment of 100,000 FPGAs in Denver, Colorado, will experience upsets in configuration memory every half-hour on average and SDC failures every 0.5–11 days on average.

scholarly journals Reduction in the number of LUT elements for control units with code sharing

2010 ◽  
Vol 20 (4) ◽  
pp. 751-761 ◽  
Author(s):  
Alexander Barkalov ◽  
Larysa Titarenko ◽  
Jacek Bieganowski
Keyword(s):  
Field Programmable Gate Arrays ◽  
Logic Circuits ◽  
Embedded Memory ◽  
Gate Arrays ◽  
Look Up Table ◽  
Control Units ◽  
Linear Chains ◽  
Code Sharing ◽  
Field Programmable ◽  
Programmable Gate Arrays

Reduction in the number of LUT elements for control units with code sharingTwo methods are proposed targeted at reduction in the number of look-up table elements in logic circuits of compositional microprogram control units (CMCUs) with code sharing. The methods assume the application of field-programmable gate arrays for the implementation of the combinational part of the CMCU, whereas embedded-memory blocks are used for implementation of its control memory. Both methods are based on the existence of classes of pseudoequivalent operational linear chains in a microprogram to be implemented. Conditions for the application of the proposed methods and examples of design are shown. Results of conducted experiments are given.

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