scholarly journals Recent Advances on the Design of High-Gain Wideband Operational Transconductance Amplifiers

VLSI Design ◽  
2009 ◽  
Vol 2009 ◽  
pp. 1-11 ◽  
Author(s):  
Rida Assaad ◽  
Jose Silva-Martinez
Keyword(s):  
High Frequency ◽  
High Gain ◽  
Feed Forward ◽  
Operational Transconductance Amplifiers ◽  
Miller Compensation ◽  
Multistage Amplifiers ◽  
Dc Gain ◽  
Folded Cascode ◽  
Transconductance Amplifiers ◽  
Better Than

Feed-forward techniques are explored for the design of high-frequency Operational Transconductance Amplifiers (OTAs). For single-stage amplifiers, a recycling folded-cascode OTA presents twice the GBW (197.2 MHz versus 106.3 MHz) and more than twice the slew rate (231.1 V/s versus 99.3 V/s) as a conventional folded cascode OTA for the same load, power consumption, and transistor dimensions. It is demonstrated that the efficiency of the recycling folded-cascode is equivalent to that of a telescopic OTA. As for multistage amplifiers, a No-Capacitor Feed-Forward (NCFF) compensation scheme which uses a high-frequency pole-zero doublet to obtain greater than 90 dB DC gain, GBW of 325 MHz and better than phase margin is discussed. The settling-time- of the NCFF topology can be faster than that of OTAs with Miller compensation. Experimental results for the recycling folded-cascode OTA fabricated in TSMC 0.18 m CMOS, and results of the NCFF demonstrate the efficiency and feasibility of the feed-forward schemes.

High Gain and High CMRR Two-Stage Folded Cascode OTA with Nested Miller Compensation

2015 ◽  
Vol 24 (04) ◽  
pp. 1550057 ◽  
Author(s):  
Meysam Akbari ◽  
Omid Hashemipour
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Open Loop ◽  
Two Stage ◽  
Miller Compensation ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Folded Cascode

By using Gm-C compensation (GCC) technique, a two-stage recycling folded cascode (FC) operational transconductance amplifier (OTA) is designed. The proposed configuration consists of recycling structure, positive feedback and feed-forward compensation path. In comparison with the typical folded cascode CMOS Miller amplifier, this design has higher DC gain, unity-gain frequency (UGF), slew rate and common mode rejection ratio (CMRR). The presented OTA is simulated in 0.18-μm CMOS technology and the simulation results confirm the theoretical analyses. Finally, the proposed amplifier has a 111 dB open-loop DC gain, 20 MHz UGF and 145 dB CMRR @ 1.2 V supply voltage while the power consumption is 400 μW which makes it suitable for low-voltage applications.

Design of High Gain Folded Cascode OTA-Based Transconductance–Capacitance Loop Filter for PLL Applications

2021 ◽  
pp. 2150263
Author(s):  
Priti Gupta ◽  
Sanjay Kumar Jana
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
High Gain ◽  
Cmos Process ◽  
Operational Transconductance Amplifier ◽  
Loop Filter ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Unity Gain ◽  
Folded Cascode

This paper deals with the designing of low-power transconductance–capacitance-based loop filter. The folded cascode-based operational transconductance amplifier (OTA) is designed in this paper with the help of quasi-floating bulk MOSFET that achieved the DC gain of 88.61[Formula: see text]dB, unity gain frequency of 97.86[Formula: see text]MHz and power consumption of 430.62[Formula: see text][Formula: see text]W. The proposed OTA is compared with the exiting OTA structure which showed 19.50% increase in DC gain and 15.11% reduction in power consumption. Further, the proposed OTA is used for the designing of transconductance–capacitance-based loop filter that has been operated at [Formula: see text]3[Formula: see text]dB cut-off frequency of 30.12[Formula: see text]MHz with the power consumption of 860.90[Formula: see text][Formula: see text]W at the supply voltage of [Formula: see text][Formula: see text]V. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process.

scholarly journals Logarithmic Slots Antennas Using Substrate Integrated Waveguide

2015 ◽  
Vol 2015 ◽  
pp. 1-11 ◽  
Author(s):  
Jahnavi Kachhia ◽  
Amit Patel ◽  
Alpesh Vala ◽  
Romil Patel ◽  
Keyur Mahant
Keyword(s):  
Dielectric Constant ◽  
High Frequency ◽  
Return Loss ◽  
High Gain ◽  
Substrate Integrated Waveguide ◽  
High Frequency Structure Simulator ◽  
High Gain Antenna ◽  
X Band ◽  
New Generation ◽  
Better Than

This paper represents new generation of slotted antennas for satellite application where the loss can be compensated in terms of power or gain of antenna. First option is very crucial because it totally depends on size of satellite so we have proposed the high gain antenna creating number of rectangular, trapezoidal, and I shape slots in logarithm size in Substrate Integrated Waveguide (SIW) structure. The structure consists of an array of various shape slots antenna designed to operate in C and X band applications. The basic structures have been designed over a RT duroid substrate with dielectric constant of 2.2 and with a thickness of 0.508 mm. Multiple slots array and shape of slot effects have been studied and analyzed using HFSS (High Frequency Structure Simulator). The designs have been supported with its return loss, gain plot, VSWR, and radiation pattern characteristics to validate multiband operation. All the proposed antennas give gain more than 9 dB and return loss better than −10 dB. However, the proposed structures have been very sensitive to their physical dimensions.

IMPROVED POWER-EFFICIENT RNMC TECHNIQUE WITH VOLTAGE BUFFER AND NULLING RESISTORS FOR LOW-POWER HIGH-LOAD THREE-STAGE AMPLIFIERS

2009 ◽  
Vol 18 (07) ◽  
pp. 1321-1331
Author(s):  
DAVIDE MARANO ◽  
GAETANO PALUMBO ◽  
SALVATORE PENNISI
Keyword(s):  
Low Power ◽  
Design Procedure ◽  
Large Signal ◽  
Power Efficient ◽  
Operational Transconductance Amplifiers ◽  
Miller Compensation ◽  
Parameter Variations ◽  
Transconductance Amplifiers ◽  
Compensation Approach ◽  
Settling Performance

This work proposes and develops an original compensation approach for low-power three-stage operational transconductance amplifiers driving large capacitive loads. The proposed solution is based on the basic reversed nested Miller compensation and exploits a voltage buffer and two nulling resistors in the compensation network, along with a feedforward stage to improve slewing and settling performance. A well-defined design procedure using the loop gain phase margin as the main design parameter is also developed. SPECTRE simulations on a three-stage amplifier are carried out and are found to be in excellent agreement with the theoretical analysis, showing a significant improvement of the proposed approach over traditional compensation strategies in terms of small-signal and large-signal performance. Monte Carlo simulation results finally prove the proposed technique to be well-guarded against process parameter variations.

Differential AC Boosting Compensation for Power-Efficient Multistage Amplifiers

2019 ◽  
Vol 15 (4) ◽  
pp. 379-387
Author(s):  
Tayebeh Asiyabi ◽  
Jafar Torfifard
Keyword(s):  
Power Dissipation ◽  
State Of The Art ◽  
Operational Transconductance Amplifier ◽  
Power Efficient ◽  
Miller Compensation ◽  
Transconductance Amplifier ◽  
Multistage Amplifiers ◽  
Dc Gain ◽  
Capacitive Load ◽  
Unity Gain

In this paper, a new architecture of four-stage CMOS operational transconductance amplifier (OTA) based on an alternative differential AC boosting compensation called DACBC is proposed. The presented structure removes feedforward and boosts feedback paths of compensation network simultaneously. Moreover, the presented circuit uses a fairly small compensation capacitor in the order of 1 pF, which makes the circuit very compact regarding enhanced several small-signal and largesignal characteristics. The proposed circuit along with several state-of-the-art schemes from the literature have been extensively analysed and compared together. The simulation results show with the same capacitive load and power dissipation the unity-gain frequency (UGF) can be improved over 60 times than conventional nested Miller compensation. The results of the presented OTA with 15 pF capacitive load demonstrated 65° phase margin, 18.88 MHz as UGF and DC gain of 115 dB with power dissipation of 462 μW from 1.8 V.

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