scholarly journals Trigger Pulse Generator Using Proposed Buffered Delay Model and Its Application

2015 ◽  
Vol 2015 ◽  
pp. 1-9 ◽  
Author(s):  
Amit Krishna Dwivedi ◽  
Kumar Abhijeet Urma ◽  
Aminul Islam
Keyword(s):  
Pulse Width ◽  
Pulse Generator ◽  
Supply Voltage ◽  
Basic Element ◽  
Trigger Pulse ◽  
Delay Model ◽  
Simulation Results ◽  
Low Supply Voltage ◽  
Application Specific ◽  
Made In

This paper proposes a circuit capable of incorporating buffered delays in the order of picoseconds. To study our proposed circuit in the profound way, we have also explored our proposed circuit using emerging technologies such as FinFET and CNFET. Comparisons between these technologies have been made in terms of different parameters such as duration of incorporated delays (pulse width) and its variability with supply voltages. Further, this paper also proposes a trigger pulse generator by utilizing proposed buffered delay circuit as its basic element. Parametric results obtained for the proposed trigger pulse generator match different application specific requirements. These applications are also mentioned in this paper. The proposed trigger pulse generator requires very low supply voltage (700 mV) and also proves its effectiveness in terms of tunability of pulse width of the generated pulses. The modeling of the circuit has been done using Verilog and the simulation results are extensively verified using SPICE.

Study on the Experimental of the Electrical Discharge Machining Titanium Alloy on Gas Dielectric

2013 ◽  
Vol 644 ◽  
pp. 171-174 ◽  
Author(s):  
Shuo Guo Zhao ◽  
Xiao Min Yao ◽  
Rui Li
Keyword(s):  
Titanium Alloy ◽  
Electrical Discharge ◽  
Pulse Width ◽  
Electrical Discharge Machining ◽  
Supply Voltage ◽  
Orthogonal Experiment ◽  
Great Influence ◽  
Gas Processing ◽  
Low Supply Voltage ◽  
Processing Properties

In order to know the processing properties of the Electrical Discharge Machining titanium alloy on gas dielectric. Firstly, this paper does comparing experiment of EDM in gas processing titanium alloy. The results indicate that electrode dissipation is low with equifrequence square wave, positive polarity and low supply voltage to machining titanium alloy when pulse width is narrow. Secondly, this paper has done the orthogonal experiment and the variance analysis of experimental results, Its result shows that pulse width and peak current have a great influence on the machining efficiency .

130 nm CMOS Bulk-Driven Variable Gain Amplifier for Low-Voltage Applications

2017 ◽  
Vol 26 (08) ◽  
pp. 1740003 ◽  
Author(s):  
Daniel Arbet ◽  
Viera Stopjaková ◽  
Martin Kováč ◽  
Lukáš Nagy ◽  
Matej Rakús ◽  
...  
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Input Voltage ◽  
Cmos Technology ◽  
Variable Gain Amplifier ◽  
Voltage Range ◽  
Variable Gain ◽  
Wide Scale ◽  
Simulation Results ◽  
Low Supply Voltage

In this paper, a variable gain amplifier (VGA) designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven (BD) design approach, which brings a possibility to operate with low supply voltage. Since the supply voltage of only 0.6 V is used for the amplifier to operate, there is no risk of latch-up event that usually represents the main drawback of the BD circuit systems. BD transistors are employed in the input differential stage, which makes it possible to operate in rail-to-rail input voltage range. Achieved simulation results indicate that gain of the proposed VGA can be varied in a wide scale, which together with the low supply voltage feature make the proposed amplifier useful for low-voltage and low-power applications. An additional circuit responsible for maintaining the linear-in-decibel gain dependency of the VGA is also addressed. The proposed circuit block avails arbitrary shaping of the curve characterizing the gain versus the controlling voltage dependency.

A High Robust SRAM Bitcell under Optimum-Energy Supply Voltage

2011 ◽  
Vol 121-126 ◽  
pp. 1332-1337
Author(s):  
Na Bai ◽  
Rui Xing Li ◽  
Zhan Li Gong ◽  
Shou Biao Tan
Keyword(s):  
Energy Supply ◽  
Supply Voltage ◽  
Threshold Region ◽  
Line Voltage ◽  
Design Changes ◽  
Optimum Energy ◽  
Sram Design ◽  
Wide Hysteresis ◽  
Simulation Results ◽  
Low Supply Voltage

Simulation results illustrate that there is an optimum-energy supply voltage point (Vopt) for SoC. And these voltage points normally lie in weak sub-threshold or near-threshold region. Considering about the degraded robustness under this low supply voltage, structural change instead of the sizing change is considered in proposed design. Different from conventional 6T SRAM design, the trip point voltage of proposed design changes according to bit-line voltage values. In this way, its read margin is 45% greater than conventional 6T SRAM. The proposed bit-cell exhibits wide hysteresis effect, making the design less vulnerable to process variation. Its hold margin is 30.2% greater than conventional 6T SRAM. The optimum-energy supply voltage of proposed array (256×16) is 400 mV. At the same time, the power consumption at 400 mV decreases to 16% compared to that at 1200 mV.

ULTRA-LOW VOLTAGE TUNABLE TRANSCONDUCTOR BASED ON BULK-DRIVEN QUASI-FLOATING-GATE TECHNIQUE

2013 ◽  
Vol 22 (08) ◽  
pp. 1350073 ◽  
Author(s):  
FABIAN KHATEB ◽  
NABHAN KHATIB ◽  
PIPAT PROMMEE ◽  
WINAI JAIKLA ◽  
LUKAS FUJCIK
Keyword(s):  
Power Consumption ◽  
Low Voltage ◽  
Supply Voltage ◽  
Floating Gate ◽  
Low Power Consumption ◽  
Mos Transistor ◽  
External Resistor ◽  
Multifunction Filter ◽  
Simulation Results ◽  
Low Supply Voltage

This paper presents ultra-low voltage transconductor using a new bulk-driven quasi-floating-gate technique (BD-QFG). This technique leads to significant increase in the transconductance and the bandwidth values of the MOS transistor (MOST) under ultra-low voltage condition. The proposed CMOS structure of the transconductor is capable to work with ultra-low supply voltage of ±300 mV and low power consumption of 18 μW. The transconductance value of the transconductor is tunable by external resistor with wide linear range. To prove the validation of the new described technique a second-order Gm-C multifunction filter is presented as one of the possible applications. The simulation results using 0.18 μm CMOS N-Well process from TSMC show the attractive features of the proposed circuit.

scholarly journals A Novel Cross-Latch Shift Register Scheme for Low Power Applications

2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Electrical Power ◽  
Average Power ◽  
Leakage Power ◽  
Shift Register ◽  
Cmos Process ◽  
Average Power Consumption ◽  
Simulation Results ◽  
Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories

1992 ◽  
Vol 27 (4) ◽  
pp. 583-588 ◽  
Author(s):  
Y. Miyawaki ◽  
T. Nakayama ◽  
S. Kobayashi ◽  
N. Ajika ◽  
M. Ohi ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Flash Memories ◽  
Low Supply Voltage

CMOS PULSE GENERATOR FOR BPSK, OOK, PAM, AND PPM MODULATIONS

2009 ◽  
Vol 18 (03) ◽  
pp. 487-495 ◽  
Author(s):  
VINCENZO STORNELLI ◽  
GIUSEPPE FERRI ◽  
KING PACE
Keyword(s):  
Remote Control ◽  
Power Consumption ◽  
Pulse Duration ◽  
Short Range ◽  
Pulse Generator ◽  
Supply Voltage ◽  
Pulse Repetition Frequency ◽  
Cmos Technology ◽  
Single Chip ◽  
Control Applications

This work presents a single chip integrated pulse generator-modulator to be utilized in a short range wireless radio sensors remote control applications. The circuit, which can generate single pulses, modulated in BPSK, OOK, PAM, and also PPM, has been developed in a standard CMOS technology (AMS 0.35 μm). Typical pulse duration is about 1 ns while pulse repetition frequency is until 200 MHz (5 ns "chip" time). The operating supply voltage is ± 2.5 V, while the whole power consumption is about 15 mW. Post-layout parametric and corner analyses have confirmed the theoretical expectations.

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