Sub-Volt Fully Balanced Differential Difference Amplifier

2014 ◽  
Vol 24 (01) ◽  
pp. 1550005 ◽  
Author(s):  
Fabian Khateb ◽  
Montree Kumngern ◽  
Spyridon Vlassis ◽  
Costas Psychalinos ◽  
Tomasz Kulej
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Cmos Technology ◽  
Floating Gate ◽  
Voltage Range ◽  
State Variable ◽  
Low Voltage Operation ◽  
Differential Difference Amplifier ◽  
Simulation Results ◽  
State Variable Filter

This paper presents a new CMOS structure for a fully balanced differential difference amplifier (FB-DDA) designed to operate from a sub-volt supply. This structure employs the bulk-driven quasi-floating-gate (BD-QFG) technique to achieve the capability of an ultra-low voltage operation and an extended input voltage range. The proposed BD-QFG FB-DDA is suitable for ultra-low-voltage low-power applications. The circuit is designed with a single supply of 0.5 V and consumes only 357 nW of power. The proposed circuit was simulated in a 0.18-μm TSMC CMOS technology and the simulation results prove its functionality and attractive parameters. An application example of a state variable filter is also presented to confirm the usefulness of the proposed BD-QFG FB-DDA.

New Schmitt Trigger with Controllable Hysteresis using Dual Control Gate-Floating Gate Transistor (DCG-FGT)

2013 ◽  
Vol 2 (1) ◽  
pp. 49
Author(s):  
Abderrezak Marzaki ◽  
V. Bidal ◽  
R. Laffont ◽  
W. Rahajandraibe ◽  
J-M. Portal ◽  
...  
Keyword(s):  
Low Voltage ◽  
Schmitt Trigger ◽  
Cmos Technology ◽  
Floating Gate ◽  
Dual Control ◽  
Switching Voltage ◽  
Voltage Range ◽  
Rail To Rail ◽  
Floating Gate Transistor ◽  
Simulation Results

This paper presents different low voltage adjustable CMOS Schmitt trigger using DCG-FGT transistor. Simple circuits are introduced to provide flexibility to program the hysteresic threshold in this paper. The hysteresis can be controlled accurately at a large voltage range. The proposed Schmitt trigger have been designed using 90nm 1.2V CMOS technology and simulated using Eldo with PSP device models. The simulation results show rail-to-rail operation and adjustable switching voltages <em>V<sub>TH- </sub></em>(low switching voltage) and <em>V<sub>TH+ </sub></em>(high switching voltage).

130 nm CMOS Bulk-Driven Variable Gain Amplifier for Low-Voltage Applications

2017 ◽  
Vol 26 (08) ◽  
pp. 1740003 ◽  
Author(s):  
Daniel Arbet ◽  
Viera Stopjaková ◽  
Martin Kováč ◽  
Lukáš Nagy ◽  
Matej Rakús ◽  
...  
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Input Voltage ◽  
Cmos Technology ◽  
Variable Gain Amplifier ◽  
Voltage Range ◽  
Variable Gain ◽  
Wide Scale ◽  
Simulation Results ◽  
Low Supply Voltage

In this paper, a variable gain amplifier (VGA) designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven (BD) design approach, which brings a possibility to operate with low supply voltage. Since the supply voltage of only 0.6 V is used for the amplifier to operate, there is no risk of latch-up event that usually represents the main drawback of the BD circuit systems. BD transistors are employed in the input differential stage, which makes it possible to operate in rail-to-rail input voltage range. Achieved simulation results indicate that gain of the proposed VGA can be varied in a wide scale, which together with the low supply voltage feature make the proposed amplifier useful for low-voltage and low-power applications. An additional circuit responsible for maintaining the linear-in-decibel gain dependency of the VGA is also addressed. The proposed circuit block avails arbitrary shaping of the curve characterizing the gain versus the controlling voltage dependency.

A 10T Cell Design without Half Select Problem for Bit-Interleaving Architecture in 65nm CMOS

2013 ◽  
Vol 373-375 ◽  
pp. 1607-1611
Author(s):  
Hong Gang Zhou ◽  
Shou Biao Tan ◽  
Qiang Song ◽  
Chun Yu Peng
Keyword(s):  
Error Correction ◽  
Low Voltage ◽  
Cmos Technology ◽  
Soft Error ◽  
Error Correction Codes ◽  
Cell Design ◽  
Low Voltage Operation ◽  
Sram Cell ◽  
Simulation Results ◽  
Nanometer Regime

With the scaling of process technologies into the nanometer regime, multiple-bit soft error problem becomes more serious. In order to improve the reliability and yield of SRAM, bit-interleaving architecture which integrated with error correction codes (ECC) is commonly used. However, this leads to the half select problem, which involves two aspects: the half select disturb and the additional power caused by half-selected cells. In this paper, we propose a new 10T cell to allow the bit-interleaving array while completely eliminating the half select problem, thus allowing low-power and low-voltage operation. In addition, the RSNM and WM of our proposed 10T cell are improved by 21% and nearly one times, respectively, as compared to the conventional 6T SRAM cell in SMIC 65nm CMOS technology. We also conduct a comparison with the conventional 6T cell about the leakage simulation results, which show 14% of leakage saving in the proposed 10T cell.

scholarly journals Design of Low Voltage Low Power High Gain Operational Transconductance Amplifier

2021 ◽  
Vol 7 (4) ◽  
pp. 103-110
Author(s):  
Rajesh Durgam ◽  
S. Tamil ◽  
Nikhil Raj
Keyword(s):  
Low Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Floating Gate ◽  
Operational Transconductance Amplifier ◽  
Linear Mode ◽  
Low Voltage Operation ◽  
Transconductance Amplifier ◽  
Amplifier Design ◽  
Self Cascode

In this paper, a high gain structure of operational transconductance amplifier is presented. For low voltage operation with improved frequency response bulk driven quasi-floating gate MOSFET is used at the input. Further for achieving high gain the modified self cascode structure is used at the output. Compared to conventional self cascode the modified self cascode structure used provides higher transconductance which helps in significant boosting of gain of the amplifier. The modification is achieved by employing quasi-floating gate transistor which helps in scaling of the threshold which as a result increases the drain-to-source voltage of linear mode transistor thus changing it to saturation. This change of mode boosts the effective transconductance of self cascode MOSFET. The proposed operational transconductance amplifier when compared to its conventional showed improvement in DC gain by 30dB and also the unity gain bandwidth increases by 6 fold. The MOS models used for amplifier design are of 0.18µm CMOS technology at supply of 0.5V.

Low-Voltage Diode-Less Rectifier Based on Fully Differential Difference Transconductance Amplifier

2017 ◽  
Vol 26 (11) ◽  
pp. 1750172 ◽  
Author(s):  
Fabian Khateb ◽  
Tomasz Kulej ◽  
Montree Kumngern ◽  
Vilém Kledrowetz
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Cmos Technology ◽  
Wearable Electronics ◽  
Voltage Range ◽  
Voltage Supply ◽  
Mos Transistor ◽  
Fully Differential ◽  
Transconductance Amplifier ◽  
Multiple Input

This paper presents a voltage-mode low-voltage low-power diode-less rectifier with only one active element, the fully differential difference transconductance amplifier (FDDTA). The multiple-input floating-gate MOS (FG-MOS) transistor is used to build the differential pairs of the FDDTA resulting in the reduced count of transistors, circuit simplicity and the capability to work under low-voltage supply with extended input voltage range. The rectifier was designed with 0.9[Formula: see text]V voltage supply and 8[Formula: see text][Formula: see text]W power consumption, hence it is suitable for wearable electronics and biomedical applications. The simulation results obtained from the Cadence platform using 0.18[Formula: see text][Formula: see text]m TSMC CMOS technology show good performances for the designed circuit.

Design Technique of High Power Efficiency LLC DC-DC Converters for Photovoltaic Cells

2018 ◽  
Vol 2 (1) ◽  
pp. 30
Author(s):  
Hisatsugu Kato ◽  
Yoichi Ishizuka ◽  
Kohei Ueda ◽  
Shotaro Karasuyama ◽  
Atsushi Ogasahara
Keyword(s):  
High Power ◽  
Power Efficiency ◽  
Photovoltaic Cells ◽  
Input Voltage ◽  
Design Technique ◽  
Load Range ◽  
Voltage Range ◽  
Simulation Results ◽  
Secondary Side ◽  
High Power Efficiency

This paper proposes a design technique of high power efficiency LLC DC-DC Converters for Photovoltaic Cells. The secondary side circuit and transformer fabrication of proposed circuit are optimized for overcoming the disadvantage of limited input voltage range and, realizing high power efficiency over a wide load range of LLC DC-DC converters. The optimized technique is described with theoretically and with simulation results. Some experimental results have been obtained with the prototype circuit designed for the 80 - 400 V input voltage range. The maximum power efficiency is 98 %.

scholarly journals Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current Range

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Low Noise ◽  
Cmos Process ◽  
Transient Time ◽  
Voltage Range ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Set Up ◽  
Ldo Regulator

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.

scholarly journals Efficiency Enhancement of Flexible Mode Bridgeless Boost Rectifier

2019 ◽  
Vol 9 (2) ◽  
pp. 1503-1508
Keyword(s):  
Power System ◽  
Input Voltage ◽  
Efficiency Enhancement ◽  
Fast Recovery ◽  
High Input ◽  
Voltage Range ◽  
Low Input ◽  
Flexible Mode ◽  
Simulation Results ◽  
Boost Rectifier

Most of the devices in power system become faulty due to the large content of harmonics present in voltage and current. It is mainly caused by the conduction losses in the system. At first, it is necessary to determine the extent of harmonic present by calculating the total harmonic distortions i.e., root over sum of the integral harmonics divide by fundamental harmonic. Later, identification of type of method for reducing harmonics is essential. In this project we are mainly focusing on two types of PFC bridge boost rectifier to improve the efficiency for low and high input voltage range. It using back to back bridgeless PFC boost rectifier for high input voltage and for low input voltage range, three level bridgeless boost rectifiers respectively. Fast recovery diode instead of normal diodes for better reliability and efficiency is utilized. The end model is obtained by combining two circuits BTBBL (Back to back bridgeless boost PFC) and TLBL (Three level bridgeless boost PFC) to get the FMBL (Flexible mode bridgeless boost PFC). Due to presence of less no of components, conduction losses are less hence less distortion is observed with improved efficiency. A simulation is carried out for all three models using MATLAB Simulink platform. In hardware, TLP250 driver for MOSFET is used and which is interfaced with PIC microcontroller. The hardware results are obtained that validates the simulation results.

FLIPPED VOLTAGE FOLLOWER ANALOG NONLINEAR CIRCUITS

2012 ◽  
Vol 21 (03) ◽  
pp. 1250024 ◽  
Author(s):  
CHAIWAT SAKUL ◽  
KOBCHAI DEJHAN
Keyword(s):  
Relative Error ◽  
Low Voltage ◽  
Harmonic Distortion ◽  
Input Voltage ◽  
Experimental Result ◽  
Voltage Range ◽  
Flipped Voltage Follower ◽  
Voltage Follower ◽  
Power Dispersion ◽  
Four Quadrant

This paper describes squaring and square-rooting circuits operable on low voltage supplies, with their application proposed hereby as vector-summation and four-quadrant multiplier circuits. These circuits make use of a flipped voltage follower (FVF) as fundamental circuit. A detail classification of basic topologies derived from the FVF is given. The proposed circuits have simple structure, wide input range and low power consumption as well as small number of devices. All circuits are also examined and supported by a set of simulations with PSpice program. The circuits can operate at power supply of ±0.7 volts, the input voltage range of the squaring circuit is ±0.8 volts with 1.59% relative error and 1.78 μW power dispersion, the input current of the square-rooting circuit is about 50 μA with 0.55% relative error and 1.4 μW power dispersion and the vector-summation circuit have linearity error of 0.23% and 2.92 μW power dispersion. As in four-quadrant multiplier circuit, the total harmonic distortion of the multiplier is less than 1.2% for 0.8 VP-P input signal at 1 MHz fundamental frequency. Experimental result is carried out to confirm the operation by using commercial CMOS transistor arrays (CD4007). These circuits are highly expected to be effective in further application of the low voltage analog signal processing.

Low Power FGSRAM Cell Using Sleepy and LECTOR Technique

2016 ◽  
Vol 4 (2) ◽  
pp. 333 ◽  
Author(s):  
Kanan Bala Ray ◽  
Sushanta Kumar Mandal ◽  
Shivalal Patro
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Stability ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Floating Gate ◽  
Power Supply Voltage ◽  
Operation Analysis ◽  
Sram Cell ◽  
Simulation Results

<em>In this paper floating gate MOS (FGMOS) along with sleep transistor technique and leakage control transistor (LECTOR) technique has been used to design low power SRAM cell. Detailed investigation on operation, analysis and result comparison of conventional 6T, FGSRAM, FGSLEEPY, FGLECTOR and FGSLEEPY LECTOR has been done. All the simulations are done in Cadence Virtuoso environment on 45 nm standard CMOS technology with 1 V power supply voltage. Simulation results show that FGSLEEPY LECTOR SRAM cell consumes very low power and achieves high stability compared to conventional FGSRAM Cell</em>

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