Fidelity of Simulation VS. Transfer of Training on a Maintenance Trainer

1982 ◽  
Vol 26 (8) ◽  
pp. 741-745 ◽  
Author(s):  
L. Bruce McDonald ◽  
Grace P. Waldrop ◽  
Richard Reynolds

Maintenance training simulators have proven to afford equal or superior training at a lower life cycle cost than actual equipment trainers when teaching troubleshooting based on front panel indications, failure symptoms and some indrawer visual indicators. The purpose of the study was to determine the effects of two-dimensional and three-dimensional fidelity of simulation and three levels of reduced accessibility to test points during training, on student troubleshooting performance while locating faults at the component level. A total of 186 students were observed and tested in the ET Splice modules of a Navy Basic Electricity and Electronics course. Conclusions are drawn about the relative training effectiveness of simulated and actual boards and recommendations are made in selecting active test points on simulated printed circuit boards.

2013 ◽  
Vol 61 (3) ◽  
pp. 731-735
Author(s):  
A.W. Stadler ◽  
Z. Zawiślak ◽  
W. Stęplewski ◽  
A. Dziedzic

Abstract. Noise studies of planar thin-film Ni-P resistors made in/on Printed Circuit Boards, both covered with two different types of cladding or uncladded have been described. The resistors have been made of the resistive-conductive-material (Ohmega-Ply©) of 100 Ώ/sq. Noise of the selected pairs of samples has been measured in the DC resistance bridge with a transformer as the first stage in a signal path. 1/f noise caused by resistance fluctuations has been found to be the main noise component. Parameters describing noise properties of the resistors have been calculated and then compared with the parameters of other previously studied thin- and thick-film resistive materials.


Author(s):  
Erik Jung ◽  
Dirk Wojakowski ◽  
Alexander Neumann ◽  
Rolf Aschenbrenner ◽  
Herbert Reichl

The demand to miniaturize products especially for mobile applications and autonomous systems is continuing to drive the evolution of electronic products and manufacturing methods. To further the miniaturization of future products the integration of functions on miniaturized subsystems, i.e. System-in-Package (SiP) is a promising approach. Here, use of recent manufacturing methods allows to merge the SiP concept with a volumetric integration of IC’s. Up to now, most of the systems make use of single- or double-sided populated system carriers. A new challenge is to incorporate not only passive components, but as well active circuitry (IC’s) and the necessary thermal management. Ultra thin chips (i.e. silicon dies thinned down to <50μm total thickness) lend themselves to reach these goals. Chips with that thickness can be embedded in the dielectric layers of modern laminate PCB’s. Micro via technology allows to contact the embedded chip to the outer faces of the system circuitry. The aspects of embedding and making the electrical contact as well as the thermal management are highlighted. Results on FEM simulations and technical achievements are presented.


10.14311/1221 ◽  
2010 ◽  
Vol 50 (4) ◽  
Author(s):  
M. Dirix ◽  
O. Koch

The development of three-dimensional printed circuit boards requires research on new materials which can easily be deformed. Conducting pastes are well suited for deformation even after they are applied to the dielectric carrier. This paper deals with measurements of the electrical conductivity of these conducting pastes. Two different conductivity measurement techniques are explained and carried out. The resulting measurements give an overview of the conductivity of several measured samples.


2020 ◽  
Vol 13 (2) ◽  
pp. 77-84
Author(s):  
Nikita Yur'ev ◽  
V. Lavlinskiy ◽  
Nadezhda Bokareva

The article analyzes the properties of conductive inks and substrates for their application. Experimental data reflecting the relationship between the chemical composition and physical properties of the ink solution are shown. The properties of electrical conductivity and ease of application to the substrate are described. This article presents a combination of filler and binder solutions in conjunction with the production technology of conductive ink. The advantages and disadvantages of various combinations of solutions and their application for further three-dimensional formation of boards are evaluated. The article describes the behavior of polymer solutions for use in existing three-dimensional printing technologies.


Author(s):  
Igor Nevliudov ◽  
Evgeny Razumov-Fryzyuk ◽  
Dmytro Nikitin ◽  
Danila Bliznyuk ◽  
Roman Strelets

The subject of research is the influence of factors of exposure of two-dimensional images on the topology of conductors in the manufacture of printed circuit boards by the method of three-dimensional polymer photomasks. The purpose of the work is ensuring the accuracy and preservation of the geometric dimensions of the conductors of printed circuit boards during LCD exposure of masks on the work piece. To achieve this goal, it is necessary to solve the following tasks: to analyze photolithography technology and types of polymer 3D printing; to develop a technological process for exposing photopolymer masks to a printed circuit board blank using 3D printing technologies; to conduct experimental studies to determine the optimal exposure parameters; on the basis of the empirical results obtained, to calculate the correlation coefficients of the factors for recall; to construct a linear regression model of the dependence of the deviations of the geometric dimensions of the printed conductors on the parameters of solutions for etching and exposure conditions. Results: The constructed regression models will become the basis for creating a software database that optimizes the initial images of the topology of printed conductors in the automated production of printed circuit boards. This will simplify the process of developing the topology of printed circuit boards, taking into account the real influence of the parameters of the technological operations of etching and exposure on the thickness of the tracks of the conductors of the printed circuit boards, which will reduce the proportion of rejects in the manufacture of single- and double-sided printed circuit boards. Conclusions: an LCD exposure technology and a method for studying the effects of exposure factors on the quality of printed circuit board topology are proposed, which provide sufficient empirical data to create regression models for calculating the influence of technological factors on the final dimensions of conductive paths in the production of printed circuit boards. Further development of the proposed technology will make it possible to manufacture rigid and flexible printed circuit boards completely, with conductive paths, a dielectric base, electronic elements that can be used in various devices.


1984 ◽  
Vol 11 (2) ◽  
pp. 109-115
Author(s):  
J. A. Scarlett

The techniques for the generation of fine lines on rigid and flexible printed circuit boards are reviewed, and it is shown how the tracking on the interconnect can be made to match the requirements of chip carriers, TAB chips or beam leaded or wire bonded chips directly mounted.The use of fine line techniques on planar substrates can be adapted to provide a low cost, high density interconnect which offers a truly three dimensional connection capability without the use of a “back wiring panel”. Such a three dimensional interconnect can offer opportunities for improvement in the removal of heat from high dissipation chips, thus offering significantly increased reliability.


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