Effect of a high-k dielectric material on the surface potential and the induced lateral field in short-channel MOSFET

2016 ◽  
pp. 403-407
Author(s):  
Akash Ganguly ◽  
Chandrima Ghosh ◽  
Arpan Deyasi
Keyword(s):  
Surface Potential ◽  
Dielectric Material ◽  
Short Channel ◽  
Lateral Field ◽  
High K ◽  
High K Dielectric

scholarly journals Performance analysis of dual material junction accumulation mode tri gate junctionless SOI FET: Modeling and Simulation

2021 ◽  
Author(s):  
Mrinmoy Goswami ◽  
Ankush Chattopadhyay ◽  
Chayanika Bose
Keyword(s):  
Surface Potential ◽  
Drain Current ◽  
Silicon On Insulator ◽  
Short Channel ◽  
Accumulation Mode ◽  
Physical Constraints ◽  
High K ◽  
Channel Effects ◽  
High K Dielectric ◽  
Dual Material

Abstract The paper illustrates the performance of Tri-Gate (TG) Dual Material (DM) SOI (Silicon on Insulator) Junctionless (JL) FET operating in Junction Accumulation Mode (JAM). An analytical model is developed to evaluate its performance. The device is also simulated using Silvaco device simulator. Both the analytical and simulation results are compared and found to match closely. Quasi 3-D modeling approach is adopted here to determine the surface potential of the above device. In this technique, the entire 3-D device is segregated into two 2-D devices with certain physical constraints. These 2-D devices are then analyzed separately to obtain the surface potentials, which are added together using suitable multiplication factors to get the surface potential of the 3-D device. This surface potential is, in turn, used to model the threshold voltage, sub-threshold drain current ( I d,sub ) and the drain induced barrier lowering (DIBL). The proposed device configuration reduces the I OFF significantly and offers excellent immunity to SCEs. The response of the proposed device is studied for the variations of certain device parameters, such as, thickness of High- K dielectric layer in stack gate, channel doping, and the workfunctions as well as lengths of the gate metals. Such study will lead to turn the proposed device immune to short channel effects through proper choice of various parameters.

scholarly journals Performance of High-k Dielectric Material for Short Channel Length MOSFET Simulated using Silvaco TCAD Tools

2021 ◽  
Vol 19 (OCT2021) ◽  
pp. 143-148
Author(s):  
Fatin Antasha Anizam ◽  
Lyly Nyl Ismail ◽  
Norsabrina Sihab ◽  
Nur Sa’adah Mohd Sauki
Keyword(s):  
Dielectric Material ◽  
Channel Length ◽  
Short Channel ◽  
High K ◽  
High K Dielectric

scholarly journals Analysis of on-off current ratio in asymmetrical junctionless double gate MOSFET using high-k dielectric materials

2021 ◽  
Vol 11 (5) ◽  
pp. 3882
Author(s):  
Hakkee Jung ◽  
Byungon Kim
Keyword(s):  
Dielectric Material ◽  
Dielectric Materials ◽  
Double Gate ◽  
Short Channel ◽  
Current Ratio ◽  
Arithmetic Average ◽  
High K ◽  
Double Gate Mosfet ◽  
High K Dielectric ◽  
High Dielectric

<span>The variation of the on-off current ratio is investigated when the asymmetrical junctionless double gate MOSFET is fabricated as a SiO<sub>2</sub>/high-k dielectric stacked gate oxide. The high dielectric materials have the advantage of reducing the short channel effect, but the rise of gate parasitic current due to the reduction of the band offset and the poor interface property with silicon has become a problem. To overcome this disadvantage, a stacked oxide film is used. The potential distributions are obtained from the Poission equation, and the threshold voltage is calculated from the second derivative method to obtain the on-current. As a result, this model agrees with the results from other papers. </span><span>The on-off current ratio is in proportion to the arithmetic average of the upper and lower high dielectric material thicknesses. The on-off current ratio of 10<sup>4</sup> or less is shown for SiO<sub>2</sub>, but the on-off current ratio for TiO<sub>2</sub> (<em>k</em>=80) increases to 10<sup>7</sup> or more.</span>

Channel hot-carrier degradation in pMOS and nMOS short channel transistors with high-k dielectric stack

2010 ◽  
Vol 87 (1) ◽  
pp. 47-50 ◽  
Author(s):  
E. Amat ◽  
T. Kauerauf ◽  
R. Degraeve ◽  
R. Rodríguez ◽  
M. Nafría ◽  
...  
Keyword(s):  
Short Channel ◽  
Hot Carrier ◽  
High K ◽  
High K Dielectric ◽  
Hot Carrier Degradation

Multiferroic Bi0.7Dy0.3FeO3 films as high k dielectric material for advanced non-volatile memory devices

2009 ◽  
Vol 45 (16) ◽  
pp. 821 ◽  
Author(s):  
K. Prashanthi ◽  
S.P. Duttagupta ◽  
R. Pinto ◽  
V.R. Palkar
Keyword(s):  
Dielectric Material ◽  
Memory Devices ◽  
High K ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
High K Dielectric

scholarly journals High-K dielectric sulfur-selenium alloys

2019 ◽  
Vol 5 (5) ◽  
pp. eaau9785 ◽  
Author(s):  
Sandhya Susarla ◽  
Thierry Tsafack ◽  
Peter Samora Owuor ◽  
Anand B. Puthirath ◽  
Jordan A. Hachtel ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Metal Oxides ◽  
High Dielectric Constant ◽  
Dielectric Material ◽  
Dielectric Strength ◽  
Dielectric Materials ◽  
High K ◽  
Device Applications ◽  
High K Dielectric ◽  
High Dielectric

Upcoming advancements in flexible technology require mechanically compliant dielectric materials. Current dielectrics have either high dielectric constant, K (e.g., metal oxides) or good flexibility (e.g., polymers). Here, we achieve a golden mean of these properties and obtain a lightweight, viscoelastic, high-K dielectric material by combining two nonpolar, brittle constituents, namely, sulfur (S) and selenium (Se). This S-Se alloy retains polymer-like mechanical flexibility along with a dielectric strength (40 kV/mm) and a high dielectric constant (K = 74 at 1 MHz) similar to those of established metal oxides. Our theoretical model suggests that the principal reason is the strong dipole moment generated due to the unique structural orientation between S and Se atoms. The S-Se alloys can bridge the chasm between mechanically soft and high-K dielectric materials toward several flexible device applications.

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