Visual tracking of a moving person for a home robot

2005 ◽  
Vol 219 (4) ◽  
pp. 259-269 ◽  
Author(s):  
Kai-Tai Song ◽  
Chen-Chu Chlen
Keyword(s):  
Visual Tracking ◽  
Tracking System ◽  
Processing System ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Human Face ◽  
Web Camera ◽  
Robot Head ◽  
Home Robot

This paper presents a visual tracking system for a home robot to pursue a person. The system works by detecting a human face and tracking a person via controlling a two-degree-of-freedom robot head and the robot body. An image processing system has been developed to extract facial features using a complementary metal-oxide semiconductor (CMOS) web camera. An algorithm is proposed to recognize a human face by using skin colour and elliptical edge information of a human face. A digital signal processing (DSP)-based motor control card is designed and implemented for robot motion control. The visual tracking control system has been integrated on a self-constructed prototype home robot. Experimental results show that the robot tracks a person in real-time.

A Quantitative Approach of Reversible Logic Gates in QCA

2015 ◽  
Vol 3 ◽  
pp. 22 ◽  
Author(s):  
Abdullah Al Shafi ◽  
Ali Newaz Bahar ◽  
Md Shifatul Islam
Keyword(s):  
Low Power ◽  
Vlsi Design ◽  
Processing System ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Cmos Technology ◽  
Reversible Logic ◽  
Oxide Semiconductor ◽  
Switching Frequency

Abstract—Quantum Dot Cellular Automata (QCA) is an eminent nano-technology and solution of Complementary Metal Oxide Semiconductor (CMOS) for it’s computation and transformation procedure. It is attractive for it’s size, faster speed, high scalable feature, low power consumption and higher switching frequency compared to CMOS technology. Reversible logic has many factual operation in QCA as well as VLSI design, nanotechnology, digital signal processing (DSP). This paper presents a systematic design of reversible gate based on QCA. A modified pattern of Fredkin gate, MCL gate and a new scheme of URG gate, BJN gate is proposed in this paper. For design and verification QCADesigner, a widely used simulation tool is employed. The proposed circuits can be used in erecting of nano scale low power information processing system and modelingcomplex computing systems.

scholarly journals Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions

Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 369 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Nikos Mastorakis
Keyword(s):  
High Speed ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Performance Comparison ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Least Significant Bit ◽  
Design Metrics ◽  
Ripple Carry Adder ◽  
Speed Performance

Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing binary-to-excess-1 code (BEC) converters. In the literature, the designs of many CLAs and CSLAs were described separately. It would be useful to have a direct comparison of their performances based on the design metrics. Hence, we implemented homogeneous and hybrid CLAs, and CSLAs with and without the BEC converters by considering 32-bit accurate and approximate additions to facilitate a comparison. For the gate-level implementations, we considered a 32/28 nm complementary metal-oxide-semiconductor (CMOS) process targeting a typical-case process–voltage–temperature (PVT) specification. The results show that the hybrid CLA/RCA architecture is preferable among the CLA and CSLA architectures from the speed and power perspectives to perform accurate and approximate additions.

scholarly journals Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic

Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 243 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Douglas Maskell ◽  
Nikos Mastorakis
Keyword(s):  
Low Power ◽  
Digital Signal Processor ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Power Design ◽  
Cmos Technology ◽  
General Purpose ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Power Cycle

Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA.

Target Recognition Application of Real-Time Optical Information Processing System

2014 ◽  
Vol 536-537 ◽  
pp. 197-200
Author(s):  
Lan Zhao ◽  
Tao Zeng
Keyword(s):  
Information Processing ◽  
Visual Tracking ◽  
Target Recognition ◽  
Tracking System ◽  
Processing System ◽  
Tracking Algorithm ◽  
Optical Information ◽  
Illumination Changes ◽  
Imaging Surveillance ◽  
Template Tracking

This paper focuses on the visual tracking algorithm in optical imaging surveillance and tracking system. The tracking particle filter framework deemed find sparse representation problem, can effectively overcome the visual tracking algorithm appears in noise, occlusion, background interference and complex situations such as illumination changes. Morphological methods using digital occlusion area is detected to determine whether the date is added to the template tracking results set, thereby updating the control template, to effectively prevent the drift tracking results.

scholarly journals Assessing MMA Welding Process Stability Using Machine Vision-Based Arc Features Tracking System

Sensors ◽  
2020 ◽  
Vol 21 (1) ◽  
pp. 84
Author(s):  
Wojciech Jamrozik ◽  
Jacek Górka
Keyword(s):  
Tracking System ◽  
Welding Process ◽  
Reference Value ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Mma Welding ◽  
Arc Length ◽  
Process Stability ◽  
Geometrical Properties ◽  
Arc Voltage

Arc length is a crucial parameter of the manual metal arc (MMA) welding process, as it influences the arc voltage and the resulting welded joint. In the MMA method, the process’ stability is mainly controlled by the skills of a welder. According to that, giving the feedback about the arc length as well as the welding speed to the welder is a valuable property at the stage of weld training and in the production of welded elements. The proposed solution is based on the application of relatively cheap Complementary Metal Oxide Semiconductor (CMOS) cameras to track the welding electrode tip and to estimate the geometrical properties of welding arc. All measured parameters are varying during welding. To validate the results of image processing, arc voltage was measured as a reference value describing in some part the process stability.

Wireless Transceiver for Three-Dimensional Integrated Circuits Using a Ring Oscillator

2019 ◽  
Vol 29 (10) ◽  
pp. 2050161
Author(s):  
Dongwoo Moon ◽  
Milim Lee ◽  
Changhyun Lee ◽  
Joung-Hu Park ◽  
Changkun Park
Keyword(s):  
Integrated Circuits ◽  
Three Dimensional ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Ring Oscillator ◽  
Oxide Semiconductor ◽  
Voltage Multiplier ◽  
Wireless Transceiver ◽  
Pulse Type

In this paper, we propose an oscillation-type transceiver for wireless chip-to-chip communication (WCC). The proposed transceiver is composed of a ring oscillator, coils, inverter-type amplifier, voltage multiplier and comparator. The ring oscillator itself acts as the on–off keying (OOK) modulator. The envelope of the transferred OOK-modulated signal is detected in the voltage multiplier of the receiver. Given that the proposed transceiver uses an OOK-modulated oscillating signal, the noise immunity is improved compared to the typical pulse-type transceiver. To verify the functionality of the proposed transceiver, we design the transceiver using the 180-nm complementary metal-oxide-semiconductor process. From the measured results, we verify that the proposed transceiver recovers the entered digital signal up to a distance of 0.2[Formula: see text]mm between the primary and secondary coils. Additionally, the sensitivity to the bias voltage of the latch is nonexistent by virtue of removing the latch in the proposed transceiver.

scholarly journals Early Output Quasi-Delay-Insensitive Array Multipliers

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 444 ◽  
Author(s):  
Balasubramanian ◽  
Maskell ◽  
Naayagi ◽  
Mastorakis
Keyword(s):  
Cycle Time ◽  
Arithmetic Operation ◽  
Data Communication ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Data Representation ◽  
Oxide Semiconductor ◽  
Array Multiplier ◽  
Array Multipliers

Multiplication is a widely used arithmetic operation in microprocessing and digital signal processing applications, and multiplication is realized using a multiplier. This article presents the quasi-delay-insensitive (QDI) early output versions of recently reported indicating asynchronous array multipliers. Delay-insensitive dual-rail encoding is used for data representation and processing, and 4-phase return-to-zero (RTZ) and return-to-one (RTO) handshake protocols are used for data communication. Many QDI array multipliers were realized using a 32/28 nm complementary metal oxide semiconductor (CMOS) technology. Compared to the optimum indicating array multiplier, the proposed optimum early output array multiplier achieves a 6.2% reduction in cycle time and a 7.4% reduction in power-cycle time product (PCTP) with respect to RTZ handshaking, and a 7.6% reduction in cycle time and an 8.8% reduction in PCTP with respect to RTO handshaking without an increase in the area. The simulation results also convey that the RTO handshaking is preferable to the RTZ handshaking for the optimum implementation of QDI array multipliers.

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