scholarly journals Analytical Performance of Low Noise Amplifier Using Single-Stage Configuration for ADS-B Receiver

2021 ◽  
Vol 21 (2) ◽  
pp. 91
Author(s):  
M. Reza Hidayat ◽  
Ilham Pazaesa ◽  
Salita Ulitia Prini
Keyword(s):  
Return Loss ◽  
Noise Figure ◽  
Impedance Matching ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Stability Factor ◽  
Ic 10 ◽  
Radar Applications ◽  
Noise Amplifier

Automatic dependent surveillance-broadcast (ADS-B) is an equipment of a radar system to reach difficult areas. For radar applications, an ADS-B requires a low noise amplifier (LNA) with high gain, stability, and a low noise figure. In this research, to produce an LNA with good performance, an LNA was designed using a BJT transistor 2SC5006 with DC bias, VCE = 3 V, and current Ic = 10 mA, also a DC supply with VCC = 12 V, to achieve a high gain with a low noise figure. The initial LNA impedance circuit was simulated using 2 elements and then converted into 3 elements to obtain parameters according to the target specification through the tuning process, impedance matching circuit was used to reduce return loss and voltage standing wave ratio (VSWR) values. The LNA sequence obtains the working frequency of 1090 MHz, return loss of -52.103 dB, a gain of 10.382, VSWR of 1.005, a noise figure of 0.552, stability factor of 0.997, and bandwidth of 83 MHz. From the simulation results, the LNA has been successfully designed according to the ADS-B receiver specifications.

scholarly journals Design and Analysis High Gain PHEMT LNA for Wireless Application at 5.8 GHz

2015 ◽  
Vol 5 (3) ◽  
pp. 611
Author(s):  
Kamil Pongot ◽  
Abdul Rani Othman ◽  
Zahriladha Zakaria ◽  
Mohamad Kadim Suaidi ◽  
Abdul Hamid Hamidon ◽  
...  
Keyword(s):  
Return Loss ◽  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Output Terminal ◽  
Wireless Application ◽  
Noise Amplifier ◽  
The Stability ◽  
Inductive Generation

This research present a design of a higher  gain (66.38dB) for PHEMT LNA  using an inductive drain feedback technique for wireless application at 5.8GHz. The amplifier it is implemented using PHEMT FHX76LP transistor devices.  The designed circuit is simulated with  Ansoft Designer SV.  The LNA was designed using  T-network as a matching technique was used at the input and output terminal,  inductive generation to the source and an inductive drain feedback. The  low noise amplifier (LNA) using lumped-component provides a noise figure 0.64 dB and a gain (S<sub>21</sub>) of 68.94 dB. The output reflection (S<sub>22</sub>), input reflection (S<sub>11</sub>) and return loss (S<sub>12</sub>) are -17.37 dB, -15.77 dB and -88.39 dB respectively. The measurement shows the  stability was at  4.54 and 3-dB bandwidth of 1.72 GHz. While, the  low noise amplifier (LNA) using  Murata manufactured component provides a noise figure 0.60 dB and a gain (S<sub>21</sub>) of 66.38 dB. The output reflection (S<sub>22</sub>), input reflection (S<sub>11</sub>) and return loss (S<sub>12</sub>) are -13.88 dB, -12.41 dB and -89.90 dB respectively. The measurement shows the  stability was at  6.81 and 3-dB bandwidth of 1.70 GHz. The input sensitivity more than -80 dBm  exceeded the standards required by IEEE 802.16.

scholarly journals A Low-Noise Amplifier Utilizing Current-Reuse Technique and Active Shunt Feedback for MedRadio Band Applications

2020 ◽  
pp. 306-316
Author(s):  
Mutanizam Abdul Mubin ◽  
◽  
Arjuna Marzuki
Keyword(s):  
Low Power ◽  
Return Loss ◽  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Cmos Process ◽  
Current Reuse ◽  
Noise Amplifier

In this work, a low-power 0.18-μm CMOS low-noise amplifier (LNA) for MedRadio applications has been designed and verified. Cadence IC5 software with Silterra’s C18G CMOS Process Design Kit were used for all design and simulation work. This LNA utilizes complementary common-source current-reuse topology and subthreshold biasing to achieve low-power operation with simultaneous high gain and low noise figure. An active shunt feedback circuit is used as input matching network to provide a suitable input return loss. For test and measurement purpose, an output buffer was designed and integrated with this LNA. Inductorless design approach of this LNA, together with the use of MOSCAPs as capacitors, help to minimize the die size. On post-layout simulations with LNA die area of 0.06 mm2 and simulated total DC power consumption of 0.5 mW, all targeted specifications are met. The simulated gain, input return loss and noise figure of this LNA are 16.3 dB, 10.1 dB and 4.9 dB respectively throughout the MedRadio frequency range. For linearity, the simulated input-referred P1dB of this LNA is -26.7 dBm while its simulated IIP3 is -18.6 dBm. Overall, the post-layout simulated performance of this proposed LNA is fairly comparable to some current state-of-the-art LNAs for MedRadio applications. The small die area of this proposed LNA is a significant improvement in comparison to those of the previously reported MedRadio LNAs.

Design of Low-Noise Two-Path Amplifier for 6–16 GHz Applications

2020 ◽  
pp. 2150136
Author(s):  
Asieh Parhizkar Tarighat ◽  
Mostafa Yargholi
Keyword(s):  
Noise Figure ◽  
Impedance Matching ◽  
High Gain ◽  
Low Noise ◽  
Cmos Process ◽  
Input Matching ◽  
Inductive Peaking ◽  
Linearity Improvement ◽  
Noise Amplifier ◽  
Path Structure

A two-path low-noise amplifier (LNA) is designed with TSMC 0.18[Formula: see text][Formula: see text]m standard RF CMOS process for 6–16[Formula: see text]GHz frequency band applications. The principle of a conventional resistive shunt feedback LNA is analyzed to demonstrate the trade-off between the noise figure (NF) and the input matching. To alleviate the mentioned issue for wideband application, this structure with noise canceling technique and linearity improvement are applied to a two-path structure. Flat and high gain is supplied by the primary path; while the input and output impedance matching are provided by the secondary path. The [Formula: see text][Formula: see text]dB bandwidth can be increased to a higher frequency by inductive peaking, which is used at the first stage of the two paths. Besides, by biasing the transistors at the threshold voltage, low power dissipation is achieved. The [Formula: see text][Formula: see text]dB gain bandwidth of the proposed LNA is 10[Formula: see text]GHz, while the maximum power gain of 13.1[Formula: see text]dB is attained. With this structure, minimum NF of 4.6[Formula: see text]dB and noise flatness of 1[Formula: see text]dB in the whole bandwidth can be achieved. The input impedance is matched, and S[Formula: see text] is lower than [Formula: see text]10 dB. With the proposed linearized LNA, the average IIP[Formula: see text][Formula: see text]dBm is gained, while it occupies 1051.7[Formula: see text][Formula: see text]m die area.

scholarly journals Design of 10 to 12 GHz Low Noise Amplifier for Ultrawideband (UWB) Syste

2018 ◽  
Vol 8 (5) ◽  
pp. 2773
Author(s):  
Toulali Islam ◽  
Lahbib Zenkouar
Keyword(s):  
Return Loss ◽  
Noise Figure ◽  
Wide Band ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Unconditionally Stable ◽  
Branch Line ◽  
Noise Amplifier

<p>Balanced amplifier is the structure proposed in this article, it provides better performance. In fact, the single amplifier meets the specification for noise figure and gain but fails to meet the return loss specification due to the large mis-matches on the input &amp; outputs. To overcome this problem one solution is to use balanced amplifier topography. In this paper, a wide-band and highgain microwave balanced amplifier constituted with branch line coupler circuit is proposed. The amplifier is unconditionally stable in the band [9-13] GHz where the gain is about 20dB. The input reflection (S11) and output return loss (S22) at 11 GHz are -33.4dB and -33.5dB respectively.</p>

scholarly journals Single Stage 180nm CMOS Low Noise Amplifier Topologies and Optimization Algorithms for S Band Frequency

2019 ◽  
Vol 8 (3) ◽  
pp. 152-157 ◽  
Keyword(s):  
Noise Figure ◽  
Optimization Algorithms ◽  
Satellite System ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Dual Band ◽  
Active Device ◽  
Band Frequency ◽  
Noise Amplifier

Low Noise Amplifier (LNA) plays an important role in radio receivers. It mainly determines the system noise and intermodulation behavior of overall receiver. LNA design is more challenging as it requires high gain, low noise figure, good input and output matching and unconditional stability. Further, designing a Low noise Amplifier requires active device selection, amplifier topology, optimization algorithms for superlative results. Hence this paper presents performance analysis of CMOS LNA based on different topologies and optimization algorithms for 180nm RF CMOS design in S band frequency. Here the best results, various limitations in each topology are reviewed and required specifications are determined in each designing. Further this best topology is used for designing LNA circuit which could be used in Indian Regional Navigation Satellite System (IRNSS) applications in dual band frequency.

scholarly journals Plug-and-play transceiver with high gain and ultra low noise figure for IEEE 802.15.4 application

2019 ◽  
Vol 32 (2) ◽  
pp. 231-238
Author(s):  
Josue Lopez-Leyva ◽  
Miguel Ponce-Camacho ◽  
Ariana Talamantes-Alvarez
Keyword(s):  
High Speed ◽  
Ieee 802.15.4 ◽  
Noise Figure ◽  
Impedance Matching ◽  
High Gain ◽  
Low Noise ◽  
Scattering Parameters ◽  
Performance Simulation ◽  
Noise Amplifier ◽  
And Performance

This paper shows the design and performance simulation of a 2.4 GHz plugand- play transceiver based on a high speed switch for IEEE 802.15.4 applications. The electrical design was optimized taking into account the scattering parameters, inputoutput impedance matching and minimum trace width. The simulation results show an important performance regarding the Noise Figure (0.38 dB) and gain (21 dB) at particular temperature for reception mode, transmission scattering parameters (S12 and S21) and reflection scattering parameters (all the rest parameters) for both mode operation (Power Amplifier and Low Noise Amplifier).

A Low Noise Amplifier with 1.1dB Noise Figure and +17dBm OIP3 for GPS RF Receivers

2013 ◽  
Vol 336-338 ◽  
pp. 1490-1495
Author(s):  
Yong Xiang ◽  
Yan Bin Luo ◽  
Ren Jie Zhou ◽  
Cheng Yan Ma
Keyword(s):  
Noise Figure ◽  
Impedance Matching ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Gain Compression ◽  
Sige Hbt ◽  
Current Consumption ◽  
Sige Bicmos ◽  
Noise Amplifier ◽  
Feedback Resistor

A 1.575GHz SiGe HBT(heterojunction bipolar transistor) low-noise-amplifier(LNA) optimized for Global Positioning System(GPS) L1-band applications was presented. The designed LNA employed a common-emitter topology with inductive emitter degeneration to simultaneously achieve low noise figure and input impedance matching. A resistor-bias-feed circuit with a feedback resistor was designed for the LNA input transistor to improve the gain compression and linearity performance. The LNA was fabricated in a commercial 0.18µm SiGe BiCMOS process. The LNA achieves a noise figure of 1.1dB, a power gain of 19dB, a input 1dB compression point(P1dB) of -13dBm and a output third-order intercept point(OIP3) of +17dBm at a current consumption of 3.6mA from a 2.8V supply.

A Fully Integrated 5.2-GHz CMOS Variable Gain LNA for 802.11a WLAN

2012 ◽  
Vol 433-440 ◽  
pp. 5579-5583
Author(s):  
Ji Hai Duan ◽  
Chun Lei Kang
Keyword(s):  
Power Supply ◽  
Return Loss ◽  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Cmos Process ◽  
Small Signal ◽  
Fully Integrated ◽  
Variable Gain ◽  
Noise Amplifier

A fully integrated 5.2GHz variable gain low noise amplifier (VGLNA) in a 0.18μm CMOS process is proposed in this paper. The VGLAN can achieve a maximum small signal gain of 17.85 dB within the noise figure (NF) of 2.04 dB and a minimum gain of 2.04 dB with good input return loss. The LNA’s P1dB in the high gain mode is -17.5 dBm. The LAN consumes only 14.58 mW from a 1.8V power supply.

STUDY OF PARASITIC CAPACITANCE EFFECT ON NOISE FIGURE OF IDCLNA IN DEEP SUBMICRON CMOS TECHNOLOGIES

2014 ◽  
Vol 23 (05) ◽  
pp. 1450058
Author(s):  
S. MANJULA ◽  
D. SELVATHI
Keyword(s):  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Current Gain ◽  
Cmos Process ◽  
Short Channel ◽  
Trade Offs ◽  
Noise Amplifier ◽  
The Impact

Low noise amplifier (LNA) is an important component in RF receiver front end. An inductively degenerated cascode low noise amplifier (IDCLNA) is mostly preferred for producing good trade-offs such as high gain, low noise figure (NF), high reverse isolation and low power consumption for narrowband applications. This IDCLNA structure is also used to reduce the gate induced noise on the noise performance by inserting the capacitance in parallel with the gate-to-source capacitance of main transistor. Usually, the parasitic overlap capacitances can impose serious constraints on achievable performance and is taken into account in IDCLNA. In this paper, IDCLNA is designed at a frequency of 2.4 GHz with analyzing the impact of parasitic overlap capacitances on IDCLNA in terms of unity current gain frequency (f T ) which will affect the NF of IDCLNA and simulated using 130 nm, 90 nm and 65 nm CMOS technologies. The NF of IDCLNA with and without parasitic overlap capacitances are analyzed and compared for different short channel CMOS processes. Simulation results show that the parasitic overlap capacitances have advantageous to reduce the gate induced noise in IDCLNA for 130-nm CMOS process for 2.4 GHz applications.

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