scholarly journals Silicone-based Chip-in-Foil System

2018 ◽  
Vol 4 (1) ◽  
pp. 131-134
Author(s):  
Lena Bleck ◽  
Andreas Heid ◽  
Rene von Metzen
Keyword(s):  
Chemical Stability ◽  
Silicone Rubber ◽  
Flip Chip ◽  
Polymer Substrate ◽  
Test Chip ◽  
Bioelectronic Medicine ◽  
Custom Made ◽  
Polymeric Encapsulation ◽  
Processing Steps ◽  
Polyimide Layer

AbstractAiming at devices for bioelectronic medicine, this paper proposes a die embedding process for the fabrication of flexible smart implants. By combining thinned bare dies with a polymeric encapsulation, completely flexible implants can be designed. The dies are encapsulated using a flip-chip process and a backfilling with silicone rubber. A completely even surface without detectable edge between the chip and the surrounding polymer substrate is achieved by gluing the chips face-down onto a polyimide-covered substrate. The backside is coated with silicone rubber and a second carrier substrate is attached. Removing the first substrate subsequent to curing of the silicone leads to chips located under a continuous polyimide layer, enabling the use of microtechnology for further processing steps. A custom-made test chip is proposed that enables the evaluation of the mechanical and chemical stability of the system.

A 10 MHz to 80 GHz BGA Transition from Chip to LTCC Interposer for Chip Scale Packages

2015 ◽  
Vol 2015 (CICMT) ◽  
pp. 000067-000072
Author(s):  
Bradley A. Thrasher ◽  
William E. McKinzie ◽  
Deepukumar M. Nair ◽  
Michael A. Smith ◽  
Allan Beikmohamadi ◽  
...  
Keyword(s):  
Insertion Loss ◽  
Flip Chip ◽  
Ball Grid Array ◽  
Electrical Performance ◽  
60 Ghz ◽  
Test Chip ◽  
Full Wave ◽  
Test Board ◽  
Measurement Results ◽  
Solder Balls

Presented here are the design, fabrication, and measurement results of a low temperature cofired ceramic (LTCC) chip-to-interposer transition utilizing a flip-chip ball grid array (BGA) interconnect that provides excellent electrical performance up to and including 80 GHz. A test board fabricated in LTCC is used as the interposer substrate and another smaller LTCC part is used as a surrogate chip for demonstration purposes. The BGA chip-to-interposer transition is designed as a back-to-back pair of transitions with an assembly consisting of an LTCC interposer, an LTCC test chip, and a BGA interconnect constructed with 260 μm diameter polymer core solder balls. The LTCC material employed is DuPont™ GreenTape™ 9K7. Full-wave simulation results predict excellent electrical performance from 10 MHz to 80 GHz, with the chip-to-interposer BGA transition having less than 0.5 dB insertion loss at 60 GHz and less than 1 dB insertion loss up to 80 GHz. In an assembled package (back-to-back BGA transitions), the insertion loss was measured to be 1 dB per transition at 60 GHz and less than 2 dB per transition for all frequencies up to 80 GHz.

O.067 Silicone-rubber moulding of custom-made cranioplasty plates

2006 ◽  
Vol 34 ◽  
pp. 19 ◽  
Author(s):  
H. Rotar ◽  
H. Stan ◽  
H. Chezan ◽  
S. Bran ◽  
S.-G. Kim ◽  
...  
Keyword(s):  
Silicone Rubber ◽  
Custom Made

Flip Chip Thermal Test Vehicle Design: Requirements, Evaluations, and Validations

2003 ◽  
Author(s):  
Teck Joo Goh ◽  
Chia-Pin Chiu ◽  
K. N. Seetharamu ◽  
G. A. Quadir ◽  
Z. A. Zainal
Keyword(s):  
Flip Chip ◽  
Printed Circuit Board ◽  
Thermal Characterization ◽  
Circuit Board ◽  
Vehicle Design ◽  
Test Chip ◽  
Test Vehicle ◽  
Design Processes ◽  
Thermal Test ◽  
Design Requirements

This paper reviews the design of a flip chip thermal test vehicle. Design requirements for different applications such as thermal characterization, assembly process optimization, and product burn-in simulation are outlined. The design processes of different thermal test chip structures including the temperature sensor and passive heaters are described in detail. In addition, the design of fireball heater, a novel test chip structure used for evaluating the effectiveness of heat spreading of advanced thermal solutions, is also illustrated. The design considerations and processes of the package substrate and printed circuit board with special emphasis on the physical routing of the thermal test chip structures are described. These design processes are supported with thermal data from various finite-element analyses (FEA) carried out to evaluate the capability and limitations of thermal test vehicle design. Design optimization as the outcome of these analyses is also elaborated. Lastly, the validation and calibration procedures of the thermal test vehicle are presented in this paper.

Analysis of A Larger Die, Copper Pillar Bump Flip Chip Package with No-Flow Underfill

2006 ◽  
Vol 3 (3) ◽  
pp. 100-108
Author(s):  
Xiaowu Zhang ◽  
D. Pinjala ◽  
E. H. Wong ◽  
Grace Chew ◽  
Zhaohui Ma ◽  
...  
Keyword(s):  
Flip Chip ◽  
Capillary Flow ◽  
Coefficient Of Thermal Expansion ◽  
Design Guidelines ◽  
Strength Data ◽  
Form Design ◽  
Parametric Studies ◽  
Cure Temperature ◽  
Packaging Cost ◽  
Processing Steps

In the flip chip assembly process, no-flow underfill (NFU) has the advantage over traditional capillary-flow underfill because of the elimination of processing steps and the reduction of packaging cost. However, currently one of the major technical obstacles in applying no-flow underfill technology is the fillet cracking of no-flow underfill during the reflow after the moisture preconditioning. In this paper, comprehensive thermo-mechanical and hygroswelling models are established to study a larger die flip chip package with no flow underfill during reflow after moisture preconditioning. The adhesion strengths between no-flow underfill and die have been characterized. Based on the modelling results and the adhesion strength data, the reason why the crack on the no-flow underfill starts and propagates, leading to fillet cracking, is also explained. A series of parametric studies are also performed to eliminate or reduce the fillet crack. The results show that a lower coefficient of thermal expansion (CTE), a lower Young's modulus (E) and a higher cure temperature of no-flow underfill are desirable for the robustness of the package. The results also show that thinner die thickness is desirable for the robustness of the package. These findings form design guidelines for the design of larger die, copper pillar bump flip chip package with no-flow underfill.

Development of Lead Free Plating Chemical for Various Applications

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000944-000967
Author(s):  
Takeshi Hatta ◽  
Atsushi Ishikawa ◽  
Takuma Katase ◽  
Akihiro Masuda
Keyword(s):  
Chemical Stability ◽  
High Speed ◽  
Flip Chip ◽  
New Technologies ◽  
High Reliability ◽  
Lead Free ◽  
Current Status ◽  
Chip Technology ◽  
Solder Bumps ◽  
Pure Sn

Flip chip connection has been applied to a lot of applications to shorten the connection length for high performance. Solder bumping is one of the key technologies for flip chip connection, and its quality strongly brings large impact on the reliability after packaging. Electroplating is one of the methods to form solder bumps. And Sn-Ag is considered as the first candidate of lead free alloy for electroplating method. We have released Sn-Ag plating chemical and it has been used by many customers in the world. In the future, flip chip technology will progress to further miniaturization and high integration with the new technologies such as Cu pillar and Through Silicon Via (TSV). At that time, further variations of alloys are necessary for electroplating method to meet various requirements. Even for Sn-Ag plating chemical, higher plating rate is required to improve productivity in mass production. In this time, we have developed new Sn-Ag high speed plating chemical based on our conventional technology. Furthermore, we have succeeded to develop Pure Sn and Sn-Cu chemicals for bumping method to meet customer's requirement. Sn-Cu is considered as a good candidate for bumping alloy to achieve high reliability, but the chemical stability is not so good. Therefore, we successfully modified the Sn-Cu chemical and extended chemical stability. We will update our current status about high speed Sn-Ag plating chemical and other chemicals like Sn-Cu and pure Sn in this time. By using these binary alloy chemicals, we are able to produce Sn-Ag-Cu solder bumps by stacking Sn-Ag and Sn-Cu. And it can bring further variation for bumping alloys.

An Approach for Characterizing Residual Mechanical Stress Caused by Packaging Processes

2006 ◽  
Vol 969 ◽  
Author(s):  
Soeren Hirsch ◽  
Bertram Schmidt
Keyword(s):  
Finite Element Method ◽  
Mechanical Stress ◽  
Flip Chip ◽  
Finite Element Method Simulation ◽  
Stress Profile ◽  
Test Chip ◽  
Resistor Network ◽  
Mems Sensor ◽  
Chip Technology ◽  
Residual Mechanical Stress

Abstractthis paper reports on a method for estimation and minimization of mechanical stress on MEMS sensor and actuator structures due to packaging processes based on flip chip technology. For studying mechanical stress a test chip with silicon membranes was fabricated. Finite element method simulation was calculate the stress profile and to determine the optimum positions for placing the resistor network.

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