scholarly journals Optimization Technique for High-Gain CMOS Power Amplifier for 5G Applications

2021 ◽  
Vol 11 (24) ◽  
pp. 11691
Author(s):  
Hayeon Jeong ◽  
Huidong Lee ◽  
Bonghyuk Park ◽  
Seunghyun Jang ◽  
Sunwoo Kong ◽  
...  
Keyword(s):  
Power Amplifier ◽  
Optimization Technique ◽  
High Gain ◽  
Common Source ◽  
Power Added Efficiency ◽  
Power Cell ◽  
Measurement Results ◽  
Saturated Output Power ◽  
The Stability ◽  
Parasitic Components

In this study, a differential power amplifier (PA) with a high gain of over 30 dB by configuring a three-stage common source unit amplifier was designed. To ensure the stability of the high-gain differential PA, the analysis to apply the capacitive neutralization method to the differential common source PA was conducted. From the analysis, the required neutralized capacitance was quantitatively calculated from the estimated parasitic components of a power cell used in the PA. To verify the feasibility of the proposed optimization technique, a Ka-band PA was designed with a 65 nm RFCMOS process. The measurement results showed a gain of 30.7 dB. The saturated output power was measured as 16.1 dBm, maximum power-added efficiency (PAE) was 29.7%, and P1dB was 13.1 dBm.

A 4.2-to-5.4 GHz stacked GaAs HBT power amplifier for C-band applications

Circuit World ◽  
2020 ◽  
Vol 46 (4) ◽  
pp. 243-248
Author(s):  
Min Liu ◽  
Panpan Xu ◽  
Jincan Zhang ◽  
Bo Liu ◽  
Liwen Zhang
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
High Power ◽  
High Efficiency ◽  
Common Source ◽  
Power Performance ◽  
Matching Network ◽  
Content Type ◽  
Power Added Efficiency ◽  
Saturated Output Power

Purpose Power amplifiers (PAs) play an important role in wireless communications because they dominate system performance. High-linearity broadband PAs are of great value for potential use in multi-band system implementation. The purpose of this paper is to present a cascode power amplifier architecture to achieve high power and high efficiency requirements for 4.2∼5.4 GHz applications. Design/methodology/approach A common emitter (CE) configuration with a stacked common base configuration of heterojunction bipolar transistor (HBT) is used to achieve high power. T-type matching network is used as input matching network. To increase the bandwidth, the output matching networks are implemented using the two L-networks. Findings By using the proposed method, the stacked PA demonstrates a maximum saturated output power of 26.2 dBm, a compact chip size of 1.17 × 0.59 mm2 and a maximum power-added efficiency of 46.3 per cent. The PA shows a wideband small signal gain with less than 3 dB variation over working frequency. The saturated output power of the proposed PA is higher than 25 dBm between 4.2 and 5.4 GHz. Originality/value The technology adopted for the design of the 4.2-to-5.4 GHz stacked PA is the 2-µm gallium arsenide HBT process. Based on the proposed method, a better power performance of 3 dB improvement can be achieved as compared with the conventional CE or common-source amplifier because of high output stacking impedance.

scholarly journals Design of W-Band GaN-on-Silicon Power Amplifier Using Low Impedance Lines

2021 ◽  
Vol 11 (19) ◽  
pp. 9017
Author(s):  
Jinho Jeong ◽  
Yeongmin Jang ◽  
Jongyoun Kim ◽  
Sosu Kim ◽  
Wansik Kim
Keyword(s):  
Power Density ◽  
Output Power ◽  
Power Amplifier ◽  
High Power ◽  
Common Source ◽  
High Electron ◽  
Large Signal ◽  
Power Added Efficiency ◽  
W Band ◽  
Gan On Si

In this paper, a high-power amplifier integrated circuit (IC) in gallium-nitride (GaN) on silicon (Si) technology is presented at a W-band (75–110 GHz). In order to mitigate the losses caused by relatively high loss tangent of Si substrate compared to silicon carbide (SiC), low-impedance microstrip lines (20–30 Ω) are adopted in the impedance matching networks. They allow for the impedance transformation between 50 Ω and very low impedances of the wide-gate transistors used for high power generation. Each stage is matched to produce enough power to drive the next stage. A Lange coupler is employed to combine two three-stage common source amplifiers, providing high output power and good input/output return loss. The designed power amplifier IC was fabricated in the commercially available 60 nm GaN-on-Si high electron mobility transistor (HEMT) foundry. From on-wafer probe measurements, it exhibits the output power higher than 26.5 dBm and power added efficiency (PAE) higher than 8.5% from 88 to 93 GHz with a large-signal gain > 10.5 dB. Peak output power is measured to be 28.9 dBm with a PAE of 13.3% and a gain of 9.9 dB at 90 GHz, which corresponds to the power density of 1.94 W/mm. To the best of the authors’ knowledge, this result belongs to the highest output power and power density among the reported power amplifier ICs in GaN-on-Si HEMT technologies operating at the W-band.

A broadband 23.1 ∼ 27.2 GHz doherty power amplifier with peak output power of 24.3 dBm

Circuit World ◽  
2019 ◽  
Vol 46 (1) ◽  
pp. 1-5
Author(s):  
Yanfeng Fang ◽  
Yijiang Zhang
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Input Power ◽  
Content Type ◽  
Fully Integrated ◽  
Power Added Efficiency ◽  
Peak Output Power ◽  
Saturated Output Power ◽  
Direct Input ◽  
Matching Techniques

Purpose This paper aims to implement a new high output power fully integrated 23.1 to 27.2 GHz gallium arsenide heterojunction bipolar transistor power amplifier (PA) to meet the stringent linearity requirements of LTE systems. Design/methodology/approach The direct input power dividing technique is used on the chip. Broadband input and output matching techniques are used for broadband Doherty operation. Findings The PA achieves a small-signal gain of 22.8 dB at 25.1 GHz and a saturated output power of 24.3 dBm at 25.1 GHz with a maximum power added efficiency of 31.7%. The PA occupies 1.56 mm2 (including pads) and consumes a maximum current of 79.91 mA from a 9 V supply. Originality/value In this paper, the author proposed a novel direct input dividing technique with broadband matching circuits using a low Q output matching technique, and demonstrated a fully-integrated Doherty PA across frequencies of 23.1∼27.2 GHz for long term evolution-license auxiliary access (LTE-LAA) handset applications.

scholarly journals Antiphase Method of the CMOS Power Amplifier Using PMOS Driver Stage to Enhance Linearity

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 103
Author(s):  
Jiwon Kim ◽  
Changhyun Lee ◽  
Jinho Yoo ◽  
Changkun Park
Keyword(s):  
Metal Oxide ◽  
Power Amplifier ◽  
Local Area Network ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Positive Sign ◽  
Common Source ◽  
Area Network ◽  
Power Added Efficiency ◽  
Power Stage

We present the possibility of a complementary metal-oxide semiconductor (CMOS) power amplifier (PA) using a driver stage composed of p-channel metal oxide semiconductor (PMOS) to enhance linearity. The PMOS driver stage is designed as a cascode structure to adapt the antiphase technique to the CMOS PA. By biasing the common-source transistor of the driver stage at the subthreshold region, we obtain a gm3 value with a positive sign to cancel out the negative gm3 of the power stage, thereby enhancing the linearity. We also investigate the effect of the bias of the cascode transistor of the driver stage on third-order intermodulation distortion and amplitude-to-phase distortion. Consequently, we show that the PMOS driver stage itself acts as a pre-distorter of the power stage. To verify the possibility of the PMOS driver stage and the proposed biasing method for the antiphase technique, we design a 2.42 GHz PA using a 180 nm RFCMOS process for wireless local area network applications. We obtain a measured maximum linear output power of 21.5 dBm with a 23.4% power-added efficiency and an error vector magnitude of 3.14%. We use an 802.11 n modulated signal with 64-quadrature amplitude modulation (QAM) (MCS7) at 65 Mb/s.

scholarly journals X-Band High-Efficiency Continuous Class B Power Amplifier GaN MMIC Assisted by Input Second-Harmonic Tuning

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1312 ◽  
Author(s):  
Chen Jin ◽  
Yuan Gao ◽  
Wei Chen ◽  
Jianhua Huang ◽  
Zhiyu Wang ◽  
...  
Keyword(s):  
Power Amplifier ◽  
Integrated Circuit ◽  
High Efficiency ◽  
Second Harmonic ◽  
Power Added Efficiency ◽  
Optimum Load ◽  
Measurement Results ◽  
Class B ◽  
Point To Point ◽  
Output Capacitance

This paper presents a high-efficiency continuous class B power amplifier MMIC (Monolithic Microwave Integrated Circuit) from 8 GHz to 10.5 GHz, fabricated with 0.25 μm GaN-on-SiC technology. The Pedro load-line method was performed to calculate the optimum load of the GaN field-effect transistor (FET) for efficiency enhancement. Optimized by an output second-harmonic tuned network, fundamental to second-harmonic impedance, mapping was established point-to-point within a broad frequency band, which approached the classic continuous class B mode with an expanded high-efficiency bandwidth. Moreover, the contribution to the output capacitance of the FET was introduced into the output second-harmonic tuned network, which simplified the structure of the output matching network. Assisted by the second-harmonic source-pull technique, the input second-harmonic tuned network was optimized to improve the efficiency of the power amplifier over the operation band. The measurement results showed 51–59% PAE (Power Added Efficiency) and 19.8–21.2 dB power gain with a saturated power of 40.8–42.2 dBm from 8 GHz to 10.5 GHz. The size of the chip was 3.2 × 2.4 mm2.

Design of a Miniaturized Class F Power Amplifier Using Capacitor Loaded Transmission Lines

Frequenz ◽  
2020 ◽  
Vol 74 (3-4) ◽  
pp. 145-152
Author(s):  
Ali Pirasteh ◽  
Saeed Roshani ◽  
Sobhan Roshani
Keyword(s):  
Power Amplifier ◽  
Mobile Communications ◽  
Transmission Lines ◽  
Low Voltage ◽  
Good Choice ◽  
Band Frequency ◽  
Power Added Efficiency ◽  
Harmonic Control ◽  
Measurement Results ◽  
Class F

AbstractIn this paper, a new method to decrease the dimensions of the microstrip structures and reducing the overall size of the class F amplifiers is presented. First, by using the PHEMT transistor with a conventional harmonic control circuit (HCC), a low-voltage class F amplifier in the L band frequency at the operating frequency of 1.75 GHz is introduced, which named primitive class F power amplifier. Then, this amplifier is optimized by using capacitor loaded transmission lines (CLTLs). The measurement results of the amplifier show that by using the CLTL structure, the overall size has been reduced 85% (0.23 λg × 0.17 λg). The maximum power-added efficiency (PAE) of the power amplifier is about 77.5 % and the power gain which has been reached to 18.33 dB. The desirable features of this power amplifier, along with its very small size, make this power amplifier a good choice to use for the global system for mobile communications.

scholarly journals Efficient technique for ultra broadband, linear power amplifier design

2012 ◽  
Vol 4 (6) ◽  
pp. 559-567 ◽  
Author(s):  
Ahmed Sayed ◽  
Sebastian Preis ◽  
Georg Boeck
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Impedance Matching ◽  
Network Synthesis ◽  
Circuit Performance ◽  
Power Added Efficiency ◽  
Starting Point ◽  
Saturated Output Power ◽  
Linear Power Amplifier ◽  
Amplifier Design

In this paper, a 10 W ultra-broadband GaN power amplifier (PA) is designed, fabricated, and tested. The suggested design technique provides a more accurate starting point for matching network synthesis and better prediction of achievable circuit performance. A negative-image model was used to fit the extracted optimum impedances based on source-/load-pull technique and multi-section impedance matching networks were designed. The implemented amplifier presents an excellent broadband performance, resulting in a gain of 8.5 ± 0.5 dB, saturated output power of ≥10 W, and power added efficiency (PAE) of ≥23% over the whole bandwidth. The linearity performance has also been characterized. An output third-order intercept point (OIP3) of ≥45 dBm was extracted based on a two-tone measurement technique in the operating bandwidth with different frequency spacing values. The memory effect based on AM/AM and AM/PM conversions was also characterized using a modulated WiMAX signal of 10 MHz bandwidth at 5.8 GHz. Furthermore, a broadband Wilkinson combiner was designed for the same bandwidth with very low loss to extend the overall output power. Excellent agreement between simulated and measured PA performances was also achieved.

scholarly journals A Wide-Band High-Gain Doherty Power Amplifier With Class-AB HEMT Amplifiers

2021 ◽  
Author(s):  
Pouya Jahanian ◽  
Azadeh Norouzi Kangarshahi
Keyword(s):  
Power Amplifier ◽  
Transmission Lines ◽  
Average Power ◽  
Wide Band ◽  
High Gain ◽  
Input Power ◽  
Power Ratio ◽  
Class Ab ◽  
Power Added Efficiency ◽  
Doherty Power Amplifier

Abstract In this paper, an attempt has been made to design a Doherty power amplifier (DPA) with high-gain and wide-band. For this purpose, two peak amplifiers are used to improve the performance of the main amplifier. Main and auxiliary amplifiers with the same structure to the class-AB type and by using micro-strip lines in place of input/output and load matching networks, transmission lines and inductors of drain and gate, that minimize the losses in the DPA. The current DPA is implemented with GaN_HEMT_CLF1G0530_100v transistor and Rogers4003 substrate, which for 1GHz frequency in 0.5-1.5GHz bandwidth will be able to be at P-1dB point (this point, input power as 30dBm and output power as 47.98dBm) increase Drain efficiency and Power added efficiency (PAE) to 81.95% and 80.73%, respectively. The DPA helps to expand the back-off region and extend the linearity region, so the Peak to average power ratio (PAPR) will be 5.21dB and the Adjacent channel power ratio (ACPR) as 58.7dBc. A gain of 17.06-17.92dB was also obtained, which is significant compared to the results of similar samples.

scholarly journals Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology

2021 ◽  
Vol 2021 ◽  
pp. 1-12
Author(s):  
Muhammad Ovais Akhter ◽  
Najam Muhammad Amin
Keyword(s):  
Low Power ◽  
Power Amplifier ◽  
Cmos Technology ◽  
High Gain ◽  
The Novel ◽  
Ultra Low Power ◽  
Design And Optimization ◽  
Power Added Efficiency ◽  
Doherty Power Amplifier ◽  
Insertion Losses

This research proposed the design and calculations of ultra-low power (ULP) Doherty power amplifier (PA) using 65 nm CMOS technology. Both the main and the peaking amplifiers are designed and optimized using equivalent lumped parameters and power combiner models. The operation has been performed in RF-nMOS subthreshold or triode region to achieve ultra-low power (ULP) and to improve the linearity of the overall power amplifier (PA). The novel design consumes a DC power of 2.1 mW, power-added efficiency (PAE) of 29.8%, operating at 2.4 GHz band, and output referred 1 dB compression point at 4.1dBm. The simulation results show a very good capability of drive current, high gain, and very low input and output insertion losses.

A 60 GHz 14 dBm power amplifier with a transformer-based power combiner in 65 nm CMOS

2011 ◽  
Vol 3 (2) ◽  
pp. 99-105 ◽  
Author(s):  
Dixian Zhao ◽  
Ying He ◽  
Lianming Li ◽  
Dieter Joos ◽  
Wim Philibert ◽  
...  
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Peak Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
60 Ghz ◽  
Power Combiner ◽  
Power Added Efficiency ◽  
Saturated Output Power

A 52–61 GHz power amplifier (PA) is implemented in 65 nm bulk complementary metal oxide semiconductor (CMOS) technology. The proposed PA employs a transformer-based power combiner to sum the output power from two unit PAs. Each unit PA uses transformer-coupled two-stage differential cascode topology. The differential cascode PA is able to increase the output power and ensure stability. The transformer-based passives enable a compact layout with the PA core area of only 0.3 mm2. The PA achieves a peak power gain of 10.2 dB with 3-dB bandwidth of 9 GHz. The measured saturated output power is 14.8 dBm with a peak power-added efficiency (PAE) of 7.2%. The reverse isolation is smaller than −33 dB from 25 to 65 GHz. The PA consumes a quiescent current of 143 mA from a 1.6 V supply.

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