scholarly journals Programmable multifunctional integrated nanophotonics

Nanophotonics ◽  
2018 ◽  
Vol 7 (8) ◽  
pp. 1351-1371 ◽  
Author(s):  
Daniel Pérez ◽  
Ivana Gasulla ◽  
José Capmany
Keyword(s):  
Low Power ◽  
Quantum Information Processing ◽  
Low Cost ◽  
Point Of View ◽  
Experimental Point ◽  
New Paradigm ◽  
Field Programmable ◽  
Spatial Regularity ◽  
Hardware Architectures ◽  
Application Fields

AbstractProgrammable multifunctional integrated nanophotonics (PMIN) is a new paradigm that aims at designing common integrated optical hardware configurations, which by suitable programming can implement a variety of functionalities that can be elaborated for basic or more complex operations in many application fields. The interest in PMIN is driven by the surge of a considerable number of emerging applications in the fields of telecommunications, quantum information processing, sensing and neurophotonics that will be calling for flexible, reconfigurable, low-cost, compact and low-power-consuming devices, much in the same way as how field programmable gate array (FPGA) devices operate in electronics. The success of PMIN relies on the research into suitable interconnection hardware architectures that can offer a very high spatial regularity as well as the possibility of independently setting (with a very low power consumption) the interconnection state of each connecting element. Integrated waveguide meshes provide regular and periodic geometries, formed by replicating a unit cell, which can take the form of a square, hexagon or triangle, among other configurations. Each side of the cell is formed by two integrated waveguides connected by means of a Mach-Zehnder interferometer (MZI) or a tunable directional coupler that can be operated by means of an output control signal as a crossbar switch or as a variable coupler with independent power division ratio and phase shift. In this paper, we review the recent advances reported in the field of PMIN and, especially, in those based on integrated photonic waveguide meshes, both from the theoretical as well as from the experimental point of view. We pay special attention to outlining the design principles, material platforms, synthesis algorithms and practical constraints of these structures and discuss their applicability to different fields.

Introduction to Programmable Integrated Photonics

2020 ◽  
pp. 1-37
Author(s):  
José Capmany ◽  
Daniel Pérez
Keyword(s):  
Integrated Circuits ◽  
Field Programmable Gate Array ◽  
Quantum Information Processing ◽  
Low Cost ◽  
Integrated Photonics ◽  
Basic Principles ◽  
Integrated Optical ◽  
Field Programmable ◽  
Application Fields ◽  
Application Specific

Programmable integrated photonics (PIP) aims at designing common integrated optical hardware configurations, which—by suitable programming—can implement a variety of functionalities that can be elaborated for basic or more complex operations in many application fields. It follows a different approach to that of application specific photonic integrated circuits (ASPICs), which have dominated during the last few decades. The interest in PIP is driven by the surge of a considerable number of emerging applications in the fields of telecommunications, quantum information processing, sensing and neurophotonics that will require flexible, reconfigurable, low-cost, compact and low-power-consuming devices, much as field programmable gate array (FPGA) devices operate in electronics. This chapter serves as a general introduction to the book and reviews the main basic principles and recent advances in PIP, including fabrication platforms, design principles, architecture choices, challenges and limitations. and provides a brief introduction to the applications of this new field.

Programmable Integrated Photonics

2020 ◽  
Author(s):  
José Capmany ◽  
Daniel Pérez
Keyword(s):  
Integrated Circuit ◽  
Performance Monitoring ◽  
Low Cost ◽  
Limiting Factors ◽  
External Control ◽  
Integrated Photonics ◽  
New Paradigm ◽  
Photonic Integrated Circuit ◽  
And Performance ◽  
Application Fields

Programmable Integrated Photonics (PIP) is a new paradigm that aims at designing common integrated optical hardware configurations, which by suitable programming can implement a variety of functionalities that, in turn, can be exploited as basic operations in many application fields. Programmability enables by means of external control signals both chip reconfiguration for multifunction operation as well as chip stabilization against non-ideal operation due to fluctuations in environmental conditions and fabrication errors. Programming also allows activating parts of the chip, which are not essential for the implementation of a given functionality but can be of help in reducing noise levels through the diversion of undesired reflections. After some years where the Application Specific Photonic Integrated Circuit (ASPIC) paradigm has completely dominated the field of integrated optics, there is an increasing interest in PIP justified by the surge of a number of emerging applications that are and will be calling for true flexibility, reconfigurability as well as low-cost, compact and low-power consuming devices. This book aims to provide a comprehensive introduction to this emergent field covering aspects that range from the basic aspects of technologies and building photonic component blocks to the design alternatives and principles of complex programmable photonics circuits, their limiting factors, techniques for characterization and performance monitoring/control and their salient applications both in the classical as well as in the quantum information fields. The book concentrates and focuses mainly on the distinctive features of programmable photonics as compared to more traditional ASPIC approaches.

scholarly journals Low-Power Pedestrian Detection System on FPGA

Proceedings ◽  
2019 ◽  
Vol 31 (1) ◽  
pp. 35 ◽  
Author(s):  
Vinh Ngo ◽  
David Castells-Rufas ◽  
Arnau Casadevall ◽  
Marc Codina ◽  
Jordi Carrabina
Keyword(s):  
Low Power ◽  
Detection System ◽  
Low Cost ◽  
Pedestrian Detection ◽  
Support Vector ◽  
Embedded Processor ◽  
Car Industry ◽  
Field Programmable ◽  
On Chip ◽  
Histogram Of Gradients

Pedestrian detection is one of the key problems in the emerging self-driving car industry. In addition, the Histogram of Gradients (HOG) algorithm proved to provide good accuracy for pedestrian detection. Many research works focused on accelerating HOG algorithm on FPGA (Field-Programmable Gate Array) due to its low-power and high-throughput characteristics. In this paper, we present an energy-efficient HOG-based implementation for pedestrian detection system on a low-cost FPGA system-on-chip platform. The hardware accelerator implements the HOG computation and the Support Vector Machine classifier, the rest of the algorithm is mapped to software in the embedded processor. The hardware runs at 50 Mhz (lower frequency than previous works), thus achieving the best pixels processed per clock and the lower power design.

scholarly journals MOCA: A Low-Power, Low-Cost Motion Capture System Based on Integrated Accelerometers

2007 ◽  
Vol 2007 ◽  
pp. 1-11 ◽  
Author(s):  
Elisabetta Farella ◽  
Luca Benini ◽  
Bruno Riccò ◽  
Andrea Acquaviva
Keyword(s):  
Low Power ◽  
Motion Capture ◽  
Gesture Recognition ◽  
Tracking System ◽  
Low Cost ◽  
Dynamic Assessment ◽  
Point Of View ◽  
Test Bed ◽  
Natural Interaction ◽  
Robust Detection

Human-computer interaction (HCI) and virtual reality applications pose the challenge of enabling real-time interfaces for natural interaction. Gesture recognition based on body-mounted accelerometers has been proposed as a viable solution to translate patterns of movements that are associated with user commands, thus substituting point-and-click methods or other cumbersome input devices. On the other hand, cost and power constraints make the implementation of a natural and efficient interface suitable for consumer applications a critical task. Even though several gesture recognition solutions exist, their use in HCI context has been poorly characterized. For this reason, in this paper, we consider a low-cost/low-power wearable motion tracking system based on integrated accelerometers called motion capture with accelerometers (MOCA) that we evaluated for navigation in virtual spaces. Recognition is based on a geometric algorithm that enables efficient and robust detection of rotational movements. Our objective is to demonstrate that such a low-cost and a low-power implementation is suitable for HCI applications. To this purpose, we characterized the system from both a quantitative point of view and a qualitative point of view. First, we performed static and dynamic assessment of movement recognition accuracy. Second, we evaluated the effectiveness of user experience using a 3D game application as a test bed.

An Overview of Multichip Module Technology for low Power Applications

1992 ◽  
Vol 264 ◽  
Author(s):  
Chung W. Ho ◽  
Sharon McAfee-Hunter
Keyword(s):  
Thin Film ◽  
Low Power ◽  
Manufacturing Process ◽  
High Performance ◽  
Low Cost ◽  
High Density ◽  
Point Of View ◽  
Multichip Module ◽  
Multichip Modules

AbstractThin-film multichip modules (i.e. MCM-D) can provide simple, low-cost packaging and interconnect options for interconnecting high-density, high-performance devices. The following is an overview of an MCM-D technology that can be implemented on top of several substrate materials. Tradeoffs will be discussed related to using different substrate materials and the corresponding implications from the assembly point of view. The MCM-D manufacturing process is reviewed and the subsequent reliability results are discussed.

Angle-sensitive pixels: a new paradigm for low-power, low-cost 2D and 3D sensing

2012 ◽  
Author(s):  
Albert Wang ◽  
Sheila S. Hemami ◽  
Alyosha Molnar
Keyword(s):  
Low Power ◽  
Low Cost ◽  
New Paradigm ◽  
3D Sensing ◽  
2D And 3D

scholarly journals Indexing structures for the PLS blockchain

Cybersecurity ◽  
2021 ◽  
Vol 4 (1) ◽  
Author(s):  
Alex Shafarenko
Keyword(s):  
Low Power ◽  
Cost Function ◽  
Data Exchange ◽  
Low Cost ◽  
Point Of View ◽  
Communication Cost ◽  
Public Key ◽  
Bitmap Index ◽  
Merkle Tree ◽  
Iot Devices

AbstractThis paper studies known indexing structures from a new point of view: minimisation of data exchange between an IoT device acting as a blockchain client and the blockchain server running a protocol suite that includes two Guy Fawkes protocols, PLS and SLVP. The PLS blockchain is not a cryptocurrency instrument; it is an immutable ledger offering guaranteed non-repudiation to low-power clients without use of public key crypto. The novelty of the situation is in the fact that every PLS client has to obtain a proof of absence in all blocks of the chain to which its counterparty does not contribute, and we show that it is possible without traversing the block’s Merkle tree. We obtain weight statistics of a leaf path on a sparse Merkle tree theoretically, as our ground case. Using the theory we quantify the communication cost of a client interacting with the blockchain. We show that large savings can be achieved by providing a bitmap index of the tree compressed using Tunstall’s method. We further show that even in the case of correlated access, as in two IoT devices posting messages for each other in consecutive blocks, it is possible to prevent compression degradation by re-randomising the IDs using a pseudorandom bijective function. We propose a low-cost function of this kind and evaluate its quality by simulation, using the avalanche criterion.

scholarly journals Low Cost Hardware Architecture of Fast Lifting Wavelet Transform for Image Compression

2019 ◽  
Vol 8 (3) ◽  
pp. 6504-6514
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Critical Path ◽  
Low Cost ◽  
Lifting Wavelet Transform ◽  
Performance Requirements ◽  
Field Programmable ◽  
Hardware Architectures ◽  
Lifting Wavelet ◽  
Hardware Efficiency

In this work, the researchers have given a low-cost, multiplier-less design with latest DWT (2D lifting technology) for high-speed dual-Z scans. A single dimension parallele row, column processors and five transposing registers are the suggested architecture. Furthermore, a 4N timeline buffer is used to process 2D DWT images with NxN resolution. Flipping architecture is intended to decrease the critical path, replacing multipliers with shifting and adding logic. To reduce transposition and latency buffers, dual Z scanning technology is introduced. The proposed architecture is better for similar performance requirements than the existing hardware architectures. Verilog is defined as the suggested Design Register Transfer Logic (RTL) and is synthesized with Xilinx ISE 14.5. When synthesized with a better hardware efficiency for Xilinx Spartan 6 series field programmable gate array, the suggested architecture works at a frequency of 140.47 MHz.

FPGA ACCELERATION FOR DNA SEQUENCE ALIGNMENT

2007 ◽  
Vol 16 (02) ◽  
pp. 245-266 ◽  
Author(s):  
GABRIEL CAFFARENA ◽  
CARLOS PEDREIRA ◽  
CARLOS CARRERAS ◽  
SLOBODAN BOJANIC ◽  
OCTAVIO NIETO-TALADRIZ
Keyword(s):  
Dna Sequence ◽  
Sequence Alignment ◽  
Dna Sequences ◽  
Low Cost ◽  
Regular Structure ◽  
Clock Frequency ◽  
Database Access ◽  
Dna Sequence Alignment ◽  
Field Programmable ◽  
Hardware Architectures

In this paper, we present two new hardware architectures that implement the Smith–Waterman algorithm for DNA sequence alignment. Previous low-cost approaches based on Field Programmable Gate Array (FPGA) technology are reviewed in detail and then improved with the goal of increased performance at the same cost (i.e., area). This goal is achieved through low level optimizations aimed to adapt the systolic structure implementing the algorithm to the regular structure of FPGAs, essentially finding the optimum granularity of the systolic cells. The proposed architectures achieve processing rates close to 1 Gbps, clearly outperforming previous approaches. Comparing to the reported FPGA results of the computation of the edit-distance between two DNA sequences, throughput is doubled for the same clock frequency with a minimum area penalty. The design has been implemented on an FPGA-based prototyping board integrated into a bioinformatics system. This has allowed validating the approach in a real system (i.e., including I/O and database access), and comparing the proposed hardware solution to purely software approaches. As shown in the paper, the results are outstanding even for slow-rate buses.

scholarly journals Controllable Optical Properties of Multiple Electromagnetically Induced Transparency in Gaseous Atomic Media

2019 ◽  
Vol 29 (1) ◽  
pp. 1 ◽  
Author(s):  
Bang Nguyen Huy ◽  
Doai Le Van ◽  
Khoa Dinh Xuan
Keyword(s):  
Optical Properties ◽  
Optical Communication ◽  
Optical Bistability ◽  
Quantum Information Processing ◽  
Electromagnetically Induced Transparency ◽  
Kerr Nonlinearity ◽  
Optical Signal ◽  
Point Of View ◽  
Experimental Point ◽  
Induced Transparency

The advent of electromagnetically induced transparency (EIT) offered a new coherent material with exotic and controllable optical properties. Although, studies on single-EIT are described in detail for single-EIT, however, extension from single- to multi- EIT is currently of current interest due to it gains advantages in multi-channel optical communication, waveguides for optical signal processing and multi-channel quantum information processing. In this work, we review recent research works concerning multi-EIT and some related applications, as controlling group velocity of light, giant Kerr nonlinearity, optical bistability. A special attention of the review also gives for analytical interpretations of EIT spectrum, its dispersion and related applications such as EIT enhanced Kerr nonlinearity and optical bistability to give physics insight. From experimental point of view, a latest development for measuring multi-EIT spectrum and its dispersion in hot medium is presented and compared to theoretical analytical representations.

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