SUPPLY VOLTAGE CONTROL OF HALL SENSORS FOR LOW POWER MAGNETO-ELECTRIC SYSTEMS

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

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A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

Journal of Low Power Electronics and Applications ◽

10.3390/jlpea11020019 ◽

2021 ◽

Vol 11 (2) ◽

pp. 19

Author(s):

Francesco Centurelli ◽

Riccardo Della Sala ◽

Pietro Monsurrò ◽

Giuseppe Scotti ◽

Alessandro Trifiletti

Keyword(s):

Low Power ◽

Low Voltage ◽

Supply Voltage ◽

Cmos Process ◽

Slew Rate ◽

Large Signal ◽

Output Stage ◽

Ultra Low Power ◽

Input Stage ◽

Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

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New CMOS shallow junction well FET structure (CMOS-SJET) for low power-supply voltage

International Technical Digest on Electron Devices Meeting ◽

10.1109/iedm.1992.307504 ◽

1992 ◽

Cited By ~ 11

Author(s):

Yoshimura ◽

Matsuoka ◽

Kakumu

Keyword(s):

Low Power ◽

Power Supply ◽

Supply Voltage ◽

Power Supply Voltage ◽

Shallow Junction

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A Low Power Low-Pass Fourth-Order Filter for WiMAX/LTE Receiver in CMOS 45nm Technology

Journal of Circuits System and Computers ◽

10.1142/s0218126617500487 ◽

2016 ◽

Vol 26 (03) ◽

pp. 1750048 ◽

Cited By ~ 1

Author(s):

Vida Orduee Niar ◽

Gholamreza Zare Fatin

Keyword(s):

Low Power ◽

Fourth Order ◽

Supply Voltage ◽

Pass Filter ◽

Low Pass Filter ◽

Power Filter ◽

Order Filter ◽

Source Follower ◽

Low Pass ◽

Circuit Technique

In this paper, a [Formula: see text]-[Formula: see text] low-pass and low power filter with tunable in-band attenuation for WiMAX/LTE receiver is presented. The fourth-order filter consists of two cascaded biquad stages. The source-follower (SF) stage is used as a key building block in these biquads. In this paper, we have presented a circuit technique to reduce the nonlinearity of the SF stage resulting from unmatched signal swings at the gate and source terminals of the input transistor. The proposed SF stage, is used for design of a linear biquad which is then utilized in a fourth-order Butterworth low-pass filter. The simulation results of the filter for bandwidth of 10 MHz show that the IIP3 of the filter is equal to 8.22[Formula: see text]dBm, in-band noise density is 100[Formula: see text]nV/[Formula: see text]Hz and power consumption is 5.9[Formula: see text]mW. The supply voltage of the filter is equal to 1[Formula: see text]V.

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