Co-development of complementary technology and modified-CPL family for organic digital integrated circuits

2015 ◽  
Vol 1795 ◽  
pp. 19-25
Author(s):  
Fabio Carta ◽  
Htay Hlaing ◽  
Hassan Edrees ◽  
Shyuan Yang ◽  
Mingoo Seok ◽  
...  
Keyword(s):  
Energy Consumption ◽  
Integrated Circuits ◽  
Organic Electronics ◽  
Gate Delay ◽  
Experimental Demonstration ◽  
Digital Integrated Circuits ◽  
New Class ◽  
Pass Transistor ◽  
Improved Performance

ABSTRACTWe present a novel logic family alternative to classic CMOS logic and its experimental demonstration for digital application of organic electronics. The proposed logic family is a modified version of the complementary pass-transistor logic (mCPL), which allows use of a stronger transistor (in our case the p-FET) to provide more of the current required to switch the capacitance in the device. We report the integration and characterization of this new class of gates and compare them with the equivalent CMOS structures. The characterization of inverters shows improved tolerance to process variation, up to 2.5× better delay, and 1.7× smaller area for the mCPL devices. Comparison of NOR and NAND gates shows 1.8× and 4.1× reduced gate delay. A 3× reduced energy consumption per operation is also simulated. The improved performance of the mCPL design makes it an alternative architecture for logic application of organic electronics.

Radiation damage characterization of digital integrated circuits

2009 ◽  
Author(s):  
Santiago Sondon ◽  
Pablo Mandolesi ◽  
Pedro Julian ◽  
Felix Palumbo ◽  
Martin Alurralde ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Radiation Damage ◽  
Digital Integrated Circuits ◽  
Damage Characterization

Some applications of electron beam microanalysis techniques in VLSI process evaluation

1983 ◽  
Vol 41 ◽  
pp. 160-161
Author(s):  
Simon Thomas
Keyword(s):  
Integrated Circuits ◽  
Process Evaluation ◽  
Large Scale ◽  
Technology Development ◽  
Analytical Techniques ◽  
Successful Implementation ◽  
Analysis Of Failures ◽  
Characterization Of Materials ◽  
Circuits Vlsi

Trends in the technology development of very large scale integrated circuits (VLSI) have been in the direction of higher density of components with smaller dimensions. The scaling down of device dimensions has been not only laterally but also in depth. Such efforts in miniaturization bring with them new developments in materials and processing. Successful implementation of these efforts is, to a large extent, dependent on the proper understanding of the material properties, process technologies and reliability issues, through adequate analytical studies. The analytical instrumentation technology has, fortunately, kept pace with the basic requirements of devices with lateral dimensions in the micron/ submicron range and depths of the order of nonometers. Often, newer analytical techniques have emerged or the more conventional techniques have been adapted to meet the more stringent requirements. As such, a variety of analytical techniques are available today to aid an analyst in the efforts of VLSI process evaluation. Generally such analytical efforts are divided into the characterization of materials, evaluation of processing steps and the analysis of failures.

TEM characterization of WSix films

1994 ◽  
Vol 52 ◽  
pp. 848-849
Author(s):  
V. C. Kannan ◽  
S. M. Merchant ◽  
R. B. Irwin ◽  
A. K. Nanda ◽  
M. Sundahl ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Vapor Deposition ◽  
High Purity ◽  
Physical Vapor Deposition ◽  
Thermal Treatments ◽  
Rapid Thermal Anneal ◽  
Tungsten Silicide ◽  
Tem Characterization ◽  
Metal Silicides

Metal silicides such as WSi2, MoSi2, TiSi2, TaSi2 and CoSi2 have received wide attention in recent years for semiconductor applications in integrated circuits. In this study, we describe the microstructures of WSix films deposited on SiO2 (oxide) and polysilicon (poly) surfaces on Si wafers afterdeposition and rapid thermal anneal (RTA) at several temperatures. The stoichiometry of WSix films was confirmed by Rutherford Backscattering Spectroscopy (RBS). A correlation between the observed microstructure and measured sheet resistance of the films was also obtained.WSix films were deposited by physical vapor deposition (PVD) using magnetron sputteringin a Varian 3180. A high purity tungsten silicide target with a Si:W ratio of 2.85 was used. Films deposited on oxide or poly substrates gave rise to a Si:W ratio of 2.65 as observed by RBS. To simulatethe thermal treatments of subsequent processing procedures, wafers with tungsten silicide films were subjected to RTA (AG Associates Heatpulse 4108) in a N2 ambient for 60 seconds at temperatures ranging from 700° to 1000°C.

Detection and Characterization of an Electrical Failure Induced during Laser Ablation of Packages

2008 ◽  
Author(s):  
P. Schwindenhammer ◽  
H. Murray ◽  
P. Descamps ◽  
P. Poirier
Keyword(s):  
Laser Ablation ◽  
Integrated Circuits ◽  
Failure Analysis ◽  
Ablation Process ◽  
Thermally Induced ◽  
Electrical Failure ◽  
Electrical Phenomenon ◽  
Semiconductor Packages ◽  
Complex Semiconductor

Abstract Decapsulation of complex semiconductor packages for failure analysis is enhanced by laser ablation. If lasers are potentially dangerous for Integrated Circuits (IC) surface they also generate a thermal elevation of the package during the ablation process. During measurement of this temperature it was observed another and unexpected electrical phenomenon in the IC induced by laser. It is demonstrated that this new phenomenon is not thermally induced and occurs under certain ablation conditions.

Characterization of Interconnect Defects Using Scanning Thermal Conductivity Microscopy

2004 ◽  
Author(s):  
H.W. Ho ◽  
J.C.H. Phang ◽  
A. Altes ◽  
L.J. Balk
Keyword(s):  
Thermal Conductivity ◽  
Integrated Circuits ◽  
Large Scale

Abstract In this paper, scanning thermal conductivity microscopy is used to characterize interconnect defects due to electromigration. Similar features are observed both in the temperature and thermal conductivity micrographs. The key advantage of the thermal conductivity mode is that specimen bias is not required. This is an important advantage for the characterization of defects in large scale integrated circuits. The thermal conductivity micrographs of extrusion, exposed and subsurface voids are presented and compared with the corresponding topography and temperature micrographs.

Emerging Techniques for the Characterization of Nano-Mechanical Properties of Integrated Circuit Components

2008 ◽  
Author(s):  
Nicholas Randall ◽  
Rahul Premachandran Nair
Keyword(s):  
Mechanical Properties ◽  
Quality Control ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Manufacturing Process ◽  
Solder Bumps ◽  
Initial Work ◽  
Circuit Components ◽  
Materials Used

Abstract With the growing complexity of integrated circuits (IC) comes the issue of quality control during the manufacturing process. In order to avoid late realization of design flaws which could be very expensive, the characterization of the mechanical properties of the IC components needs to be carried out in a more efficient and standardized manner. The effects of changes in the manufacturing process and materials used on the functioning and reliability of the final device also need to be addressed. Initial work on accurately determining several key mechanical properties of bonding pads, solder bumps and coatings using a combination of different methods and equipment has been summarized.

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