scholarly journals A Study on the Variable Inductor Design by Switching the Main Paths and the Coupling Coils

Electronics ◽  
2021 ◽  
Vol 10 (15) ◽  
pp. 1856
Author(s):  
Yen-Chung Chiang ◽  
Juo-Chen Chen ◽  
Yu-Hsin Chang
Keyword(s):  
Design Method ◽  
The Other ◽  
Cmos Process ◽  
Mos Transistors ◽  
Quality Factors ◽  
Process Technology ◽  
Variation Versus ◽  
Variable Inductor ◽  
Metal Layers ◽  
Coupled Coils

In a radio frequency (RF) system, it is possible to use variable inductors for providing tunable or selective frequency range. Variable inductors can be implemented by the microelectromechanical system (MEMS) process or by using transistors as switches to change the routing of coils or coupling quantities. In this paper, we investigated the design method of a variable inductor by using MOS transistors to switch the main coil paths and the secondary coupled coils. We observed the effects of different metal layers, turn numbers, and layout arrangements for secondary-coupled coils and compared their characteristics on the inductances and quality factors. We implemented two chips in the 0.18 m CMOS process technology for each kind of arrangement for verification. One inductor can achieve inductance values from about 300 pH to 550 pH, and the other is between 300 pH and 575 pH, corresponding to 59.3% and 62.5%, respectively, inductance variation range at 4 GHz frequency. Additionally, their fine step sizes of the switched inductances are from 0.5% to 6% for one design, and 1% to 12.5% for the other. We found that both designs achieved a large inductance tuning range and moderate inductance step sizes with a slight difference behavior on the inductance variation versus frequency.

64-BIT PIPELINE CARRY LOOKAHEAD ADDER USING ALL-N-TRANSISTOR TSPC LOGICS

2006 ◽  
Vol 15 (01) ◽  
pp. 13-27 ◽  
Author(s):  
KUO-HSING CHENG ◽  
SHUN-WEN CHENG ◽  
WEN-SHIUAN LEE
Keyword(s):  
Supply Voltage ◽  
Internal Node ◽  
Cmos Process ◽  
Clock Frequency ◽  
Mos Transistors ◽  
Power Performance ◽  
Process Technology ◽  
Operation Speed ◽  
Circuit Techniques ◽  
Full Swing

This paper proposes two improved circuit techniques of True Single-Phase Clocking (TSPC) logic, which called Nonfull Swing TSPC (NSTSPC) and All-N-TSPC (ANTSPC). The voltage of internal node of the NSTSPC is not full swing; it saves partial dynamic power dissipation. And the ANTSPC uses NMOS transistors to replace PMOS transistors, the output loading of Φ-section is therefore reduced and a higher layout density is obtained. Through postlayout simulation comparisons between number of stacked MOS transistors and delay time, and supply voltage vs maximum frequency, the proposed NSTSPC and ANTSPC circuits show better operation speed and power performance than the conventional TSPC circuit. Finally, the new TSPC circuits are applied to a 64-bit hierarchical pipeline Carry Lookahead Adder (CLA), which based on TSMC 0.35 μm CMOS process technology. By using the techniques of NSTSPC and ANTSPC alternately, the 64-bit CLA is successfully implemented as a pipelined structure. The results of post-layout simulation show that the 64-bit CLA can be operated on 1.25 GHz clock frequency and its power/maximal frequency ratio is 151.4 μW/MHz.

SRAM Failure Analysis Strategy

2003 ◽  
Author(s):  
P. Egger ◽  
C. Burmer
Keyword(s):  
Liquid Crystal ◽  
Failure Analysis ◽  
The Other ◽  
Other Hand ◽  
Analysis Strategy ◽  
Emission Microscopy ◽  
Metal Layers ◽  
Failure Localization

Abstract The area of embedded SRAMs in advanced logic ICs is increasing more and more. On the other hand smaller structure sizes and an increasing number of metal layers make conventional failure localization by using emission microscopy or liquid crystal inefficient. In this paper a SRAM failure analysis strategy will be presented independent on layout and technology.

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

scholarly journals A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Sensors ◽  
2021 ◽  
Vol 21 (7) ◽  
pp. 2260
Author(s):  
Khuram Shehzad ◽  
Deeksha Verma ◽  
Danial Khan ◽  
Qurat Ul Ain ◽  
Muhammad Basim ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Intelligent Transportation System ◽  
Cmos Process ◽  
Process Technology ◽  
Back Issue ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Switching Method

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

Design and Evaluation of Usable Systems

2002 ◽  
Vol 46 (3) ◽  
pp. 367-371
Author(s):  
John F. McGrew
Keyword(s):  
Genetic Algorithm ◽  
Change Management ◽  
Management System ◽  
Design Method ◽  
The Other ◽  
Design Team ◽  
Style Analysis ◽  
Decision Style ◽  
Parallel Design

This paper discusses a case study of a design and evaluation of a change management system at a large Telecommunications Corporation. The design and evaluation were done using the facilitated genetic algorithm (a parallel design method) and user decision style analysis. During the facilitated genetic algorithm the design team followed the procedure of the genetic algorithm. Usability was evaluated by applying user decision style analysis to the designed system. The design is compared with an existing system and with one designed by an analyst. The change management system designed by the facilitated genetic algorithm took less time to design and decision style analysis indicated it would be easier to use than the other two systems.

scholarly journals A 219-µW ultra-low power low-noise amplifier for IEEE 802.15.4 based battery powered, portable, wearable IoT applications

2021 ◽  
Vol 3 (4) ◽  
Author(s):  
S. Chrisben Gladson ◽  
Adith Hari Narayana ◽  
V. Thenmozhi ◽  
M. Bhaskar
Keyword(s):  
Low Power ◽  
Ieee 802.15.4 ◽  
Low Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Process Technology ◽  
Ultra Low Power ◽  
Power Mode ◽  
Noise Amplifier

AbstractDue to the increased processing data rates, which is required in applications such as fifth-generation (5G) wireless networks, the battery power will discharge rapidly. Hence, there is a need for the design of novel circuit topologies to cater the demand of ultra-low voltage and low power operation. In this paper, a low-noise amplifier (LNA) operating at ultra-low voltage is proposed to address the demands of battery-powered communication devices. The LNA dual shunt peaking and has two modes of operation. In low-power mode (Mode-I), the LNA achieves a high gain ($$S21$$ S 21 ) of 18.87 dB, minimum noise figure ($${NF}_{min.}$$ NF m i n . ) of 2.5 dB in the − 3 dB frequency range of 2.3–2.9 GHz, and third-order intercept point (IIP3) of − 7.9dBm when operating at 0.6 V supply. In high-power mode (Mode-II), the achieved gain, NF, and IIP3 are 21.36 dB, 2.3 dB, and 13.78dBm respectively when operating at 1 V supply. The proposed LNA is implemented in UMC 180 nm CMOS process technology with a core area of $$0.40{\mathrm{ mm}}^{2}$$ 0.40 mm 2 and the post-layout validation is performed using Cadence SpectreRF circuit simulator.

Buckling Design of Axially Compressed Cylindrical Shells Based on Energy Barrier Approach

2021 ◽  
pp. 2150165
Author(s):  
Haigui Fan ◽  
Wenguang Gu ◽  
Longhua Li ◽  
Peiqi Liu ◽  
Dapeng Hu
Keyword(s):  
Experimental Data ◽  
Energy Barrier ◽  
Thin Shell ◽  
Design Method ◽  
Lightweight Design ◽  
Cylindrical Shells ◽  
Design Criterion ◽  
The Other ◽  
Shell Structures ◽  
Buckling Loads

Buckling design of axially compressed cylindrical shells is still a challenging subject considering the high imperfection-sensitive characteristic in this kind of structure. With the development of various design methods, the energy barrier concept dealing with buckling of imperfection-sensitive cylindrical shells exhibits a promising prospect in recent years. In this study, buckling design of imperfection-sensitive cylindrical shells under axial compression based on the energy barrier approach is systematically investigated. The methodology about buckling design based on the energy barrier approach is described in detail first taking advantage of the cylindrical shells whose buckling loads have been extensively tested. Then, validation and discussion about this buckling design method have been carried out by the numerical and experimental analyses on the cylindrical shells with different geometrical and boundary imperfections. Results in this study together with the available experimental data have verified the reliability and advantage of the buckling design method based on energy barrier approach. A design criterion based on the energy barrier approach is therefore established and compared with the other criteria. Results indicate that buckling design based on energy barrier approach can be used as an efficient way in the lightweight design of thin-shell structures.

Interaction Between Low Temperatures Spacers and Source Drain Extensions and Pockets for Both NMOS and PMOS of the 65 nm Node Technology

2006 ◽  
Vol 912 ◽  
Author(s):  
Nathalie Cagnat ◽  
Cyrille Laviron ◽  
Daniel Mathiot ◽  
Pierre Morin ◽  
Frédéric Salvetti ◽  
...  
Keyword(s):  
Oxide Layer ◽  
Hydrogen Content ◽  
Low Temperatures ◽  
Direct Contact ◽  
Fabrication Process ◽  
Experimental Results ◽  
The Other ◽  
Mos Transistors ◽  
Phosphorus Source ◽  
Activation Annealing

AbstractDuring the MOS transistors fabrication process, the source-drain extension areas are directly in contact with the oxide liner of the spacers stack. In previous works [1, 2, 3] it has been established that boron can diffuse from the source-drain extensions into the spacer oxide liner during the subsequent annealing steps, and that the amount of boron loss depends on the hydrogen content in the oxide, because it enhances B diffusivity in SiO2.In order to characterize and quantify the above phenomena, we performed test experiments on full sheet samples, which mimic either BF2 source-drain extensions over arsenic pockets implants, or BF2 pockets under arsenic or phosphorus source-drain extensions implants. Following the corresponding implants, the wafers were covered with different spacer stacks (oxide + nitride) deposited either by LPCVD, or PECVD. After appropriate activation annealing steps, SIMS measurements were used to characterize the profiles of the various dopants, and the corresponding dose loss was evaluated for each species.Our experimental results clearly evidence that LPCVD or PECVD spacer stacks have no influence on the arsenic profiles. On the other hand, phosphorus and boron profiles are affected. For boron profiles, each spacer type has a different influence. It is also shown that boron out-diffuses not only from the B doped source-drain extension in direct contact with the oxide layer, but also from the "buried" B pockets lying under n-doped source drain extension areas. All these results are discussed in term of the possible relevant mechanism.

scholarly journals Novel Design of Low-Power High-Speed Hybrid Full Adder Design using Gate Diffusion Input (GDI) Technique

2020 ◽  
Vol 9 (12) ◽  
pp. 323-328
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Circuit Simulation ◽  
Full Adder ◽  
Cmos Process ◽  
Path Delay ◽  
Process Technology ◽  
Xnor Gate

VLSI technology become one of the most significant and demandable because of the characteristics like device portability, device size, large amount of features, expenditure, consistency, rapidity and many others. Multipliers and Adders place an important role in various digital systems such as computers, process controllers and signal processors in order to achieve high speed and low power. Two input XOR/XNOR gate and 2:1 multiplexer modules are used to design the Hybrid Full adders. The XOR/XNOR gate is the key punter of power included in the Full adder cell. However this circuit increases the delay, area and critical path delay. Hence, the optimum design of the XOR/XNOR is required to reduce the power consumption of the Full adder Cell. So a 6 New Hybrid Full adder circuits are proposed based on the Novel Full-Swing XOR/XNOR gates and a New Gate Diffusion Input (GDI) design of Full adder with high-swing outputs. The speed, power consumption, power delay product and driving capability are the merits of the each proposed circuits. This circuit simulation was carried used cadence virtuoso EDA tool. The simulation results based on the 90nm CMOS process technology model.

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