scholarly journals Oxide Degradation Effects in Dry Patterning of Resist Using Neutral Oxygen Beams

1992 ◽  
Vol 268 ◽  
Author(s):  
Walter E. Mlynko ◽  
Srinandan R. Kasi ◽  
Dennis M. Manos
Keyword(s):  
Dielectric Breakdown ◽  
Electrical Characterization ◽  
Plasma Source ◽  
Interface State ◽  
State Density ◽  
Low Energy ◽  
Carrier Injection ◽  
Polysilicon Gate ◽  
Atomic Beams ◽  
Novel Processing

ABSTRACTNovel processing methods are being studied to address the highly selective and directional etch requirements of the ULSI manufacturing era; neutral molecular and atomic beams are two promising candidates. In this study, the potential of 5 eV neutral atomic oxygen beams for dry development of photoresist is demonstrated for application in patterning of CMOS devices. The patterning of photoresist directly on polysilicon gate layers enables the use of a self-contained dry processing strategy, with oxygen beams for resist etching and chlorine beams for polysilicon etching. Exposure to such reactive low-energy species and to the UV radiation from the line-of-sight, high-density plasma source can, however, alter MOSFET gate oxide quality, impacting device performance and reliability. We have studied this process-related device integrity issue by subjecting polysilicon gate MOS structures to exposure treatments of 5–20 eV oxygen beams similar to those used for resist patterning. Electrical characterization shows a significant increase in the oxide trapped charge (30–90x) and interface state density (30–60x) upon low-energy exposure. Current-voltage(IV) and dielectric breakdown characterization show increased low-field leakage characteristics for the same exposure. High-field electron injection studies reveal that the 0.25–V to 0.5–V negative flatband shifts (measured after oxygen beam exposure) can be partially annealed by carrier injection. This could be due to positive charge annihilation or electron trapping, or some combination of both. SEM and electrical analysis of structures exposed to neutral beam processing are presented along with the results of thermal annealing treatments.

A STUDY OF THE ELECTRICAL PROPERTIES OF Al2O3 FILMS DEPOSITED ON GaAs SUBSTRATES BY SPRAY PYROLYSIS

2002 ◽  
Vol 09 (05n06) ◽  
pp. 1637-1640 ◽  
Author(s):  
J. CHAVEZ-RAMIREZ ◽  
M. AGUILAR-FRUTIS ◽  
M. GARCIA ◽  
E. MARTINEZ ◽  
O. ALVAREZ-FREGOSO ◽  
...  
Keyword(s):  
Aluminum Oxide ◽  
Spray Pyrolysis ◽  
Electric Fields ◽  
Dielectric Breakdown ◽  
Spray Pyrolysis Technique ◽  
Interface State ◽  
State Density ◽  
Oxide Semiconductor ◽  
Electrical Characteristics ◽  
Gaas Substrates

Electrical characteristics of high quality aluminum oxide thin films deposited by the spray pyrolysis technique on GaAs substrates are reported. The films were deposited using a spraying solution of aluminum acetylacetonate in N,N-dimethylformamide and an ultrasonic mist generator. The substrates were (100) GaAs wafers Si-doped (1018 cm -3). The substrate temperature during deposition was in the range of 300–600°C. The electrical characteristics of these films were determined by capacitance and current versus voltage measurements by the incorporation of these films into metal-oxide-semiconductor structures. The interface state density resulted in the order of 1012 1/ eV-cm 2 and the films can stand electric fields higher than 5 MV/cm, without observing a destructive dielectric breakdown. The refractive index, measured by ellipsometry at 633 nm, resulted close to 1.64. The determination of the chemical composition of the films was achieved by energy dispersive X-ray spectroscopy; it resulted close to that of stoichiometric aluminum oxide (O/Al = 1.5) when films are deposited at substrate temperatures of 300–350°C.

Electrical Properties of High-K LaLuO3 Gate Oxide for SOI MOSFETs

2011 ◽  
Vol 276 ◽  
pp. 87-93
Author(s):  
Y.Y. Gomeniuk ◽  
Y.V. Gomeniuk ◽  
A. Nazarov ◽  
P.K. Hurley ◽  
Karim Cherkaoui ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Gate Oxide ◽  
Interface State ◽  
Channel Length ◽  
State Density ◽  
Interface State Density ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Threshold Voltages

The paper presents the results of electrical characterization of MOS capacitors and SOI MOSFETs with novel high-κ LaLuO3 dielectric as a gate oxide. The energy distribution of interface state density at LaLuO3/Si interface is presented and typical maxima of 1.2×1011 eV–1cm–2 was found at about 0.25 eV from the silicon valence band. The output and transfer characteristics of the n- and p-MOSFET (channel length and width were 1 µm and 50 µm, respectively) are presented. The front channel mobility appeared to be 126 cm2V–1s–1 and 70 cm2V–1s–1 for n- and p-MOSFET, respectively. The front channel threshold voltages as well as the density of states at the back interface are presented.

FT-IR, Sims and Electrical Characterization of Si3N4 Thin Films Obtained from C.V.D. Assisted by In-Situ Electrical Discharge

1992 ◽  
Vol 284 ◽  
Author(s):  
B. Balland ◽  
J. C. Bureau ◽  
C. Plossu ◽  
R. Botton
Keyword(s):  
Thin Films ◽  
Electrical Discharge ◽  
Low Frequency ◽  
Electrical Characterization ◽  
Interface State ◽  
State Density ◽  
Flat Band ◽  
Band Shift ◽  
Ft Ir

ABSTRACTAn original process has been developed enabling the fabrication of CVD insulating (Si3N4) thin films, by means of an in-situ activation of the reactions at T < 400°C and under P=1 to 2 torr. Mono-Si substrates were nitrided using a mixture of argon containing SiH4 and NH3·O2 has also been added to the reaction gases. The activation was performed by a DC electrical discharge. The substrate was not used as an electrode and was placed parallel to the discharge current. This configuration minimized the contamination of the films during their formation. The obtained layers have been analyzed using FT-IR and SIMS.M.I.S. structures have been realized, and the flat-band shift ΔVFB and the interface state density Nit have been extracted from the high and low frequency C-V characteristics. The values of the flat-band shift depend on the discharge domain and decrease with temperature. Good electrical characteristics are obtained for thin films formed at low temperature.

scholarly journals Electrical Characterization of Si/ZnO Nanorod PN Heterojunction Diode

2020 ◽  
Vol 2020 ◽  
pp. 1-9 ◽  
Author(s):  
Sadia Muniza Faraz ◽  
Wakeel Shah ◽  
Naveed Ul Hassan Alvi ◽  
Omer Nur ◽  
Qamar Ul Wahab
Keyword(s):  
Conduction Band ◽  
Zno Nanorods ◽  
Electrical Characterization ◽  
Interface State ◽  
State Density ◽  
Average Height ◽  
Zno Nanorod ◽  
Heterojunction Diode ◽  
Rectification Factor

The electrical characterization of p-Silicon (Si) and n-Zinc oxide (ZnO) nanorod heterojunction diode has been performed. ZnO nanorods were grown on p-Silicon substrate by the aqueous chemical growth (ACG) method. The SEM image revealed high density, vertically aligned hexagonal ZnO nanorods with an average height of about 1.2 μm. Electrical characterization of n-ZnO nanorods/p-Si heterojunction diode was done by current-voltage (I-V), capacitance-voltage (C-V), and conductance-voltage (G-V) measurements at room temperature. The heterojunction exhibited good electrical characteristics with diode-like rectifying behaviour with an ideality factor of 2.7, rectification factor of 52, and barrier height of 0.7 V. Energy band (EB) structure has been studied to investigate the factors responsible for small rectification factor. In order to investigate nonidealities, series resistance and distribution of interface state density (NSS) below the conduction band (CB) were extracted with the help of I-V and C-V and G-V measurements. The series resistances were found to be 0.70, 0.73, and 0.75 KΩ, and density distribution interface states from 8.38 × 1012 to 5.83 × 1011 eV−1 cm−2 were obtained from 0.01 eV to 0.55 eV below the conduction band.

Fabrication of High Quality MOS Devices for Application in Hazardous Environments Based on RTP Gate Dielectrics with In Situ RTCVD of Polysilicon Gates

1993 ◽  
Vol 300 ◽  
Author(s):  
B. Fröschle ◽  
H.P. Bruemmer ◽  
W. Lang ◽  
K. Neumeier ◽  
P. Ramm
Keyword(s):  
Threshold Voltage ◽  
Gate Dielectrics ◽  
Chemical Vapor ◽  
Process Variations ◽  
Interface State ◽  
State Density ◽  
Breakdown Field ◽  
Polysilicon Gate ◽  
Radiation Induced

ABSTRACTProcess modules for MOS gate fabrication were developed which can be completed subsequently in one RTP reactor: atmospheric process sequences for gate oxides and oxynitrides as well as low pressure chemical vapor deposition of polysilicon (RTCVD). Prior to the Rapid Thermal Oxidation (RTO), the wafers were treated with a Rapid Thermal Cleaning process (RTC) in H2/Ar ambient. After the desoxidation step the RTO was done in O2/H2/Ar followed by an anneal (RTA) for the gate oxide or a nitridation in NH3 (RTN) and reoxidation for the oxynitrides, respectively. The polysilicon gate electrode was fabricated either by RTCVD in situ or in a conventional furnace reactor. The two-step RTCVD process resulted in a very good thickness uniformity for the polysilicon layers of 3% (3mm from the edge). The influence of the process variations on breakdown field, fixed oxide charge, interface state density, flatband voltage, and threshold voltage of the different types of gate dielectrics was investigated. The charges and voltages were determined by LF-HF CV measurements. In order to characterize the radiation tolerance of electronic devices, radiation induced flatband and threshold voltage shifts as well as the build up of interface charges were determined. The irradiation was performed at a Co - 60 gamma source. Breakdown fields in the range of 19 MV/cm, interface state densities of less than 109 eV−1cm−2, and radiation induced threshold voltage shifts below 0.1 V after 1.5 Mrad(Si) were obtained.

Enhanced Gate Oxide Reliability through Fluorine Incorporation and the Influence of Polysilicon Process Variations

1991 ◽  
Vol 225 ◽  
Author(s):  
K. P. MacWilliams ◽  
L. E. Lowry ◽  
S. T. Lin ◽  
M. Song ◽  
R. Cole ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Low Frequency ◽  
Process Variations ◽  
Interface State ◽  
State Density ◽  
Apparent Lack ◽  
Hot Carrier ◽  
Quality And Reliability ◽  
Fluorinated Oxides ◽  
The Impact

ABSTRACTThere has been some uncertainty as to the impact of fluorine (F) on SiO2 quality and reliability. Several laboratories have shown greatly enhanced quality and reliability with fluorinated oxides, while others have been unable to repeat the results. In addition, the laboratories which have shown enhanced reliability with the fluorinated oxides have differed in their interpretation of the mechanism by which the enhancement occurs. X-ray diffraction stress measurements, partial time dependent dielectric breakdown (TDDB) measurements, SIMS depth profiling, transmission electron microscopy, standard high/low frequency C-V measurements, and hot-carrier aging of variously processed MOSFETs have been used to investigate a variety of fluorinated films. We believe that the apparent lack of consistency of the effects of fluorine on MOSFET reliability between laboratories may be explained by slight variations in the gate polysilicon processing which result in variations in polysilicon morphology. The polysilicon morphology determines both mechanical stress and F diffusion which ultimately impacts interface state density and thus hot carrier reliability.

Electrical Characterization and Reliability of Nitrided-Gate Insulators for N- and P-Type 4H-SiC MIS Devices

2010 ◽  
Vol 645-648 ◽  
pp. 825-828 ◽  
Author(s):  
Masato Noborio ◽  
Michael Grieb ◽  
Anton J. Bauer ◽  
Dethard Peters ◽  
Peter Friedrichs ◽  
...  
Keyword(s):  
High Performance ◽  
Electrical Characterization ◽  
Interface State ◽  
State Density ◽  
Channel Mobility ◽  
Gate Insulators ◽  
Interface Characteristics ◽  
Mis Devices ◽  
P Type ◽  
Mis Capacitors

In this paper, nitrided insulators such as N2O-grown oxides, deposited SiO2 annealed in N2O, and deposited SiNx/SiO2 annealed in N2O on thin-thermal oxides have been investigated for realization of high performance n- and p-type 4H-SiC MIS devices. The MIS capacitors were utilized to evaluate MIS interface characteristics and the insulator reliability. The channel mobility was determined by using the characteristics of planar MISFETs. Although the N2O-grown oxides are superior to the dry O2-grown oxides, the deposited SiO2 and the deposited SiNx/SiO2 exhibited lower interface state density (n-MIS: below 7x1011 cm-2eV-1 at EC-0.2 eV, p-MIS: below 6x1011 cm-2eV-1 at EV+0.2 eV) and higher channel mobility (n-MIS: over 25 cm2/Vs, p-MIS: over 10 cm2/Vs). In terms of reliability, the deposited SiO2 annealed in N2O exhibits a high charge-to-breakdown over 50 C/cm2 at room temperature and 15 C/cm2 at 200°C. The nitrided-gate insulators formed by deposition method have superior characteristics than the thermal oxides grown in N2O.

scholarly journals Barrier Modification by Methyl Violet Organic Dye Molecules of Ag/P-Inp Structures

2016 ◽  
Vol 2 (3) ◽  
pp. 7 ◽  
Author(s):  
Ömer Güllü
Keyword(s):  
Barrier Height ◽  
Methyl Violet ◽  
Electrical Characterization ◽  
Interface State ◽  
State Density ◽  
Mis Structure ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Mis Diode

This work includes fabrication and electrical characterization of Metal/Interlayer/Semiconductor (MIS) structures with methyl violet organic film on p-InP wafer. Metal(Ag)/ Interlayer (methyl violet =MV)/Semiconductor(p-InP) MIS structure presents a rectifying contact behavior. The values of ideality factor (n) and barrier height (BH) for the Ag/MV/p-InP MIS diode by using the current-voltage (I-V) measurement have been extracted as 1.21 and 0.84 eV, respectively. It was seen that the BH value of 0.84 eV calculated for the Ag/MV/p-InP MIS structure was significantly higher than the value of 0.64 eV of Ag/p-InP control contact. This situation was ascribed to the fact that the MV organic interlayer increased the effective barrier height by influencing the space charge region of inorganic semiconductor. The values of diffusion potential and barrier height for the Ag/MV/p-InP MIS diode by using the capacitance-voltage (C-V) measurement have been extracted as 1.21 V and 0.84 eV, respectively. The interface-state density of the Ag/MV/p-InP structure was seen to change from 2.57×1013 eV-1cm-2 to 2.19×1012 eV-1cm-2.

Characterization of Metal-Oxide-Silicon Interface by Monoenergetic Positron Beam

1992 ◽  
Vol 262 ◽  
Author(s):  
Yuzuru Ohji ◽  
Akira Uedono ◽  
Long Wei ◽  
Yasushi Tabuki ◽  
Shoichiro Tanigawa
Keyword(s):  
Electric Field ◽  
Positron Annihilation ◽  
Dielectric Breakdown ◽  
Positron Beam ◽  
Interface State ◽  
Carrier Injection ◽  
State Generation ◽  
Silicon Interface ◽  
Mos Device

ABSTRACTMOS device interfaces are investigated using carrier injection and monoenergetic positron beam experiments. Carrier injection reveals that the holes injected into gate S1O2 film seem to be the main cause of the interface state generation and the dielectric breakdown of thin-gate SiO2. Positron annihilation experiments show that the positron diffuse along the electric field in the Si and the gate SiO2 and are trapped in the interface region before annihilation. The obtained value of 5 at the SiO2/Si interface was 0.500 ±0.003. The behavior of holes in the SiO2 and SiO2/Si interface are simulated using the monoenergetic positron annihilation technique.

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