Electrical Characterization and Reliability of Nitrided-Gate Insulators for N- and P-Type 4H-SiC MIS Devices

In this paper, nitrided insulators such as N2O-grown oxides, deposited SiO2 annealed in N2O, and deposited SiNx/SiO2 annealed in N2O on thin-thermal oxides have been investigated for realization of high performance n- and p-type 4H-SiC MIS devices. The MIS capacitors were utilized to evaluate MIS interface characteristics and the insulator reliability. The channel mobility was determined by using the characteristics of planar MISFETs. Although the N2O-grown oxides are superior to the dry O2-grown oxides, the deposited SiO2 and the deposited SiNx/SiO2 exhibited lower interface state density (n-MIS: below 7x1011 cm-2eV-1 at EC-0.2 eV, p-MIS: below 6x1011 cm-2eV-1 at EV+0.2 eV) and higher channel mobility (n-MIS: over 25 cm2/Vs, p-MIS: over 10 cm2/Vs). In terms of reliability, the deposited SiO2 annealed in N2O exhibits a high charge-to-breakdown over 50 C/cm2 at room temperature and 15 C/cm2 at 200°C. The nitrided-gate insulators formed by deposition method have superior characteristics than the thermal oxides grown in N2O.

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Electrical Properties of High-K LaLuO3 Gate Oxide for SOI MOSFETs

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.276.87 ◽

2011 ◽

Vol 276 ◽

pp. 87-93

Author(s):

Y.Y. Gomeniuk ◽

Y.V. Gomeniuk ◽

A. Nazarov ◽

P.K. Hurley ◽

Karim Cherkaoui ◽

...

Keyword(s):

Electrical Characterization ◽

Gate Oxide ◽

Interface State ◽

Channel Length ◽

State Density ◽

Interface State Density ◽

Mos Capacitors ◽

Channel Mobility ◽

Threshold Voltages

The paper presents the results of electrical characterization of MOS capacitors and SOI MOSFETs with novel high-κ LaLuO3 dielectric as a gate oxide. The energy distribution of interface state density at LaLuO3/Si interface is presented and typical maxima of 1.2×1011 eV–1cm–2 was found at about 0.25 eV from the silicon valence band. The output and transfer characteristics of the n- and p-MOSFET (channel length and width were 1 µm and 50 µm, respectively) are presented. The front channel mobility appeared to be 126 cm2V–1s–1 and 70 cm2V–1s–1 for n- and p-MOSFET, respectively. The front channel threshold voltages as well as the density of states at the back interface are presented.

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Enhanced Channel Mobility in 4H-SiC MISFETs by Utilizing Deposited SiN/SiO2 Stack Gate Structures

Materials Science Forum ◽

10.4028/www.scientific.net/msf.600-603.679 ◽

2008 ◽

Vol 600-603 ◽

pp. 679-682 ◽

Cited By ~ 7

Author(s):

Masato Noborio ◽

Jun Suda ◽

Tsunenobu Kimoto

Keyword(s):

Interface State ◽

State Density ◽

Interface State Density ◽

Post Deposition Annealing ◽

Interface Quality ◽

Channel Mobility ◽

Capacitance Voltage ◽

Mis Capacitors ◽

Post Deposition ◽

Time Lead

Deposited SiN/SiO2 stack gate structures have been investigated to improve the 4H-SiC MOS interface quality. Capacitance-voltage measurements on fabricated SiN/SiO2 stack gate MIS capacitors have indicated that the interface state density is reduced by post-deposition annealing in N2O at 1300°C. The usage of thin SiN and increase in N2O-annealing time lead to a low interface state density of 1×1011 cm-2eV-1 at EC – 0.2 eV. Oxidation of the SiN during N2O annealing has resulted in improvement of SiC MIS interface. The fabricated SiN/SiO2 stack gate MISFETs demonstrate a high channel mobility of 32 cm2/Vs on (0001)Si face and 40 cm2/Vs on (000-1)C face.

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Effect of Post-Oxidation Annealing in Wet O2 and N2O Ambient on Thermally Grown SiO2/4H-SiC Interface for P-Channel MOS Devices

Materials Science Forum ◽

10.4028/www.scientific.net/msf.717-720.709 ◽

2012 ◽

Vol 717-720 ◽

pp. 709-712 ◽

Cited By ~ 5

Author(s):

Shuji Katakami ◽

Manabu Arai ◽

Kensuke Takenaka ◽

Yoshiyuki Yonezawa ◽

Hitoshi Ishimori ◽

...

Keyword(s):

Interfacial Properties ◽

Interface State ◽

State Density ◽

Interface State Density ◽

Promising Method ◽

Mos Capacitors ◽

Channel Mobility ◽

Mos Devices ◽

Inversion Channel ◽

P Type

We investigated the effect of post-oxidation annealing in wet O2 and N2O ambient, following dry O2 oxidation on the SiC MOS interfacial properties by using p-type MOS capacitors. The interfacial properties were dramatically improved by the introduction of hydrogen or nitrogen atoms into the SiO2/SiC interface, in each POA process. Notably, the N2O-POA process at 1200 °C or higher reduced the interface state density more effectively than the wet-O2-POA process, and offers a promising method to further improve the inversion channel mobility of p-channel SiC MOS devices.

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Interface-State-Density Evaluation of p-type and n-type Ge/GeNx Structures by Conductance Technique

IEEJ Transactions on Electronics Information and Systems ◽

10.1541/ieejeiss.133.1279 ◽

2013 ◽

Vol 133 (7) ◽

pp. 1279-1284

Author(s):

Takuro Iwasaki ◽

Toshiro Ono ◽

Yohei Otani ◽

Yukio Fukuda ◽

Hiroshi Okamoto

Keyword(s):

Interface State ◽

State Density ◽

Interface State Density ◽

Conductance Technique ◽

Density Evaluation ◽

P Type

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Demonstration of a Robust All-Silicon-Carbide Intracortical Neural Interface

Micromachines ◽

10.3390/mi9080412 ◽

2018 ◽

Vol 9 (8) ◽

pp. 412 ◽

Cited By ~ 9

Author(s):

Evans Bernardin ◽

Christopher Frewin ◽

Richard Everly ◽

Jawad Ul Hassan ◽

Stephen Saddow

Keyword(s):

Silicon Carbide ◽

High Performance ◽

Electrical Characterization ◽

Electrode Impedance ◽

Voltage Range ◽

Promising Solution ◽

Multiple Materials ◽

Diode Behavior ◽

Materials Used ◽

P Type

Intracortical neural interfaces (INI) have made impressive progress in recent years but still display questionable long-term reliability. Here, we report on the development and characterization of highly resilient monolithic silicon carbide (SiC) neural devices. SiC is a physically robust, biocompatible, and chemically inert semiconductor. The device support was micromachined from p-type SiC with conductors created from n-type SiC, simultaneously providing electrical isolation through the resulting p-n junction. Electrodes possessed geometric surface area (GSA) varying from 496 to 500 K μm2. Electrical characterization showed high-performance p-n diode behavior, with typical turn-on voltages of ~2.3 V and reverse bias leakage below 1 nArms. Current leakage between adjacent electrodes was ~7.5 nArms over a voltage range of −50 V to 50 V. The devices interacted electrochemically with a purely capacitive relationship at frequencies less than 10 kHz. Electrode impedance ranged from 675 ± 130 kΩ (GSA = 496 µm2) to 46.5 ± 4.80 kΩ (GSA = 500 K µm2). Since the all-SiC devices rely on the integration of only robust and highly compatible SiC material, they offer a promising solution to probe delamination and biological rejection associated with the use of multiple materials used in many current INI devices.

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Determination of Interface-State Distributions in Polymer-Based Metal-Insulator-Semiconductor Capacitors by Impedance Spectroscopy

Applied Sciences ◽

10.3390/app8091493 ◽

2018 ◽

Vol 8 (9) ◽

pp. 1493 ◽

Cited By ~ 6

Author(s):

Hideyuki Hatta ◽

Yuhi Miyagawa ◽

Takashi Nagase ◽

Takashi Kobayashi ◽

Takashi Hamada ◽

...

Keyword(s):

Impedance Spectroscopy ◽

Field Effect Transistors ◽

Interface State ◽

Interface States ◽

Localized States ◽

Electrical Performance ◽

Metal Insulator ◽

Metal Insulator Semiconductor ◽

Gate Insulators ◽

Mis Capacitors

Information on localized states at the interfaces of solution-processed organic semiconductors and polymer gate insulators is critical to the development of printable organic field-effect transistors (OFETs) with good electrical performance. This paper reports on the use of impedance spectroscopy to determine the energy distribution of the density of interface states in organic metal-insulator-semiconductor (MIS) capacitors based on poly(3-hexylthiophene) (P3HT) with three different polymer gate insulators, including polyimide, poly(4-vinylphenol), and poly(methylsilsesquioxane). The findings of the study indicate that the impedance characteristics of the P3HT MIS capacitors are strongly affected by patterning and thermal annealing of the organic semiconductor films. To extract the interface-state distributions from the conductance of the P3HT MIS capacitors, an equivalent circuit model with continuum trap states is used, which also takes the band-bending fluctuations into consideration. In addition, the relationship between the determined interface states and the electrical characteristics of P3HT-based OFETs is investigated.

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Oxide Degradation Effects in Dry Patterning of Resist Using Neutral Oxygen Beams

MRS Proceedings ◽

10.1557/proc-268-41 ◽

1992 ◽

Vol 268 ◽

Cited By ~ 3

Author(s):

Walter E. Mlynko ◽

Srinandan R. Kasi ◽

Dennis M. Manos

Keyword(s):

Dielectric Breakdown ◽

Electrical Characterization ◽

Plasma Source ◽

Interface State ◽

State Density ◽

Low Energy ◽

Carrier Injection ◽

Polysilicon Gate ◽

Atomic Beams ◽

Novel Processing

ABSTRACTNovel processing methods are being studied to address the highly selective and directional etch requirements of the ULSI manufacturing era; neutral molecular and atomic beams are two promising candidates. In this study, the potential of 5 eV neutral atomic oxygen beams for dry development of photoresist is demonstrated for application in patterning of CMOS devices. The patterning of photoresist directly on polysilicon gate layers enables the use of a self-contained dry processing strategy, with oxygen beams for resist etching and chlorine beams for polysilicon etching. Exposure to such reactive low-energy species and to the UV radiation from the line-of-sight, high-density plasma source can, however, alter MOSFET gate oxide quality, impacting device performance and reliability. We have studied this process-related device integrity issue by subjecting polysilicon gate MOS structures to exposure treatments of 5–20 eV oxygen beams similar to those used for resist patterning. Electrical characterization shows a significant increase in the oxide trapped charge (30–90x) and interface state density (30–60x) upon low-energy exposure. Current-voltage(IV) and dielectric breakdown characterization show increased low-field leakage characteristics for the same exposure. High-field electron injection studies reveal that the 0.25–V to 0.5–V negative flatband shifts (measured after oxygen beam exposure) can be partially annealed by carrier injection. This could be due to positive charge annihilation or electron trapping, or some combination of both. SEM and electrical analysis of structures exposed to neutral beam processing are presented along with the results of thermal annealing treatments.

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Inversion channel mobility and interface state density of diamond MOSFET using N-type body with various phosphorus concentrations

Applied Physics Letters ◽

10.1063/1.5100328 ◽

2019 ◽

Vol 114 (24) ◽

pp. 242101 ◽

Cited By ~ 6

Author(s):

Tsubasa Matsumoto ◽

Hiromitsu Kato ◽

Toshiharu Makino ◽

Masahiko Ogura ◽

Daisuke Takeuchi ◽

...

Keyword(s):

Interface State ◽

State Density ◽

Interface State Density ◽

Channel Mobility ◽

Inversion Channel

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MBE Growth of Oxides for III–N MOSFETs

MRS Proceedings ◽

10.1557/proc-573-247 ◽

1999 ◽

Vol 573 ◽

Cited By ~ 5

Author(s):

B. Gila ◽

K N. Lee ◽

J Laroche ◽

F Ren ◽

S. M. Donovan ◽

...

Keyword(s):

Thermal Stability ◽

High Performance ◽

Gate Dielectric ◽

Field Effect Transistors ◽

Electrical Characterization ◽

Dielectric Materials ◽

Interface State ◽

Oxide Semiconductor ◽

Good Thermal Stability ◽

Deposition Conditions

ABSTRACTReproducible fabrication of high performance metal oxide semiconductor field effect transistors (MOSFETs) from compound semiconductors will require both good interfacial electrical characteristics and good thermal stability. While dielectrics such as SiO2, AIN, and GdGaOx have demonstrated low to moderate interface state densities, questions remain about their thermal stability and reliability, particularly for use in high power or high temperature widebandgap devices. In this paper we will compare the utility of two potential gate dielectric materials: GdOx and GaOx. GdOx has been found to produce layers with excellent surface morphologies as evidenced by surface roughness of less than I nm. Stoichiometric films can be easily obtained over a range of deposition conditions, though deposition temperatures of 500°C appear to offer the optimum interfacial electrical quality. By contrast GaOx films are quite rough, polycrystalline and show poor thermal stability. Further they exhibit a range of stoichiometries depending upon deposition temperature, Ga flux and oxygen flux. This paper will describe the relationship between deposition conditions and film characteristics for both materials, and will present electrical characterization of capacitors fabricated from GdOx on Si.

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