Capacitance-Voltage, Current Voltage, and Thermal Stability of Copper Alloyed With Aluminum or Magnesium

1998 ◽  
Vol 514 ◽  
Author(s):  
T. Suwwan de Felipe ◽  
S. P. Murarka ◽  
S. Bedell ◽  
W. A. Lanford
Keyword(s):  
Thermal Treatment ◽  
Integrated Circuits ◽  
Pure Copper ◽  
Oxide Semiconductor ◽  
Silicon Substrates ◽  
Current Voltage ◽  
Resistance To Oxidation ◽  
Silicon Integrated Circuits ◽  
Capacitance Voltage ◽  
Copper Aluminum

ABSTRACTCopper alloyed with small amounts of aluminum or magnesium has recently been suggested as a promising material for interconnect applications in silicon integrated circuits. This work reports the results of the investigation of the electrical (capacitance-voltage and current-voltage) stability of the metal-oxide-semiconductor capacitor made with copper-0.5 at. % aluminum and copper-2 at. % magnesium as metal, deposited on thermally oxidized silicon substrates. Effect of thermal treatment in vacuum ambient before and/or during the electrical testing was investigated. The resistance to oxidation of these alloys was also investigated. The results show that copper magnesium, after a thermal treatment of 350°C or higher, produces a passivating layer at the interfaces that has excellent corrosion resistance and very stable behavior in terms of capacitance-voltage and current-voltage measurements. Copper aluminum performed adequately, much better than pure copper but was inferior to copper magnesium.

Low Temperature High Quality Growth of Silicon-Dioxide Using Oxygenation of Hydrogenation-Assisted Nano-Structured Silicon Thin Films

2007 ◽  
Vol 989 ◽  
Author(s):  
Nima Rouhi ◽  
Behzad Esfandyarpour ◽  
Shams Mohajerzadeh ◽  
Pouya Hashemi ◽  
Bahman Hekmat-Shoar ◽  
...  
Keyword(s):  
Thin Films ◽  
Low Temperature ◽  
Oxidation Process ◽  
Oxide Semiconductor ◽  
Silicon Substrates ◽  
High Quality ◽  
Silicon Thin Films ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Mos Structures

AbstractWe report a low temperature high quality oxide growth of nano-structured silicon thin films on silicon substrates obtained through a hydrogenation-assisted PECVD technique followed by a plasma enhanced oxidation process. The deposited layers were investigated and compared with respect to their electrical, optical and stoichiometrical properties by means of Ellipsometry, Rutherford backscattering (RBS), Raman spectroscopy, Fourier transform infrared (FTIR) spectroscopy, and by current voltage and capacitance voltage measurements on metal-oxide-semiconductor (MOS) structures.

Characterization of Nanocrystalline p-CuO/n-Si Hetrojunction Prepared by RF-Sputtering

2014 ◽  
Vol 1024 ◽  
pp. 120-123
Author(s):  
Nezar Gassem Elfadill ◽  
M. Roslan Hashim ◽  
Khaled M. Chahrour ◽  
Chun Sheng Wang
Keyword(s):  
Cupric Oxide ◽  
Pure Copper ◽  
Rf Sputtering ◽  
Saturation Current ◽  
Font Size ◽  
X Ray Diffraction ◽  
Single Crystalline ◽  
Current Voltage ◽  
Capacitance Voltage

Normal 0 false false false EN-US X-NONE AR-SA /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Calibri","sans-serif";}Nanocrystalline cupric oxide (CuO) film was prepared by sputtering of pure copper metal on n-type single crystalline Si substrate under argon-oxygen ambient. Structural and morphological analyses of the as-deposited CuO films were performed by X-ray diffraction (XRD) diffractometer and Field Emission Scanning Electron Microscopy (FESEM). The results show Single crystalline granular nanocrystalline (002) CuO films, with 18 nm crystallite size. Current-voltage (I-V) and capacitance-voltage (C-V) measurements were performed for p-CuO/n-Si hetrojunction. Diode parameters such as saturation current (Is=9.5E-6 A) and ideality factor (n=1.86) were extracted from the dark I-V characteristics. Potential barrier height of the junction (ϕi=1.1V) was revealed from (1/C2- V) plot. Normal 0 false false false EN-US X-NONE AR-SA /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Calibri","sans-serif";}

A novel route for the synthesis of Sr1−xBaxNb2O6 thin films

1995 ◽  
Vol 10 (10) ◽  
pp. 2404-2407 ◽  
Author(s):  
A. Kashani ◽  
M.S. Tomar ◽  
E. Dayalan
Keyword(s):  
Thin Films ◽  
Spin Coating ◽  
Annealing Temperature ◽  
Precursor Solution ◽  
Crystalline Material ◽  
Silicon Substrates ◽  
Silicon Structure ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Niobium Ethoxide

Stoichiometric Sr1−xBaxNb2O6 (SBN) powder and thin films were prepared by a chemical method. The starting materials were niobium ethoxide and the hydroxides of strontium and barium. Powders were obtained by evaporation of the precursor solution, and thin films were deposited by spin coating. Annealing temperature required to obtain complete conversion to the crystalline material was about 700 °C. Stoichiometric polycrystalline films of Sr1−xBaxNb2O6 were deposited on quartz and silicon substrates. Leakage current-voltage and the capacitance-voltage measurements on a metal/SBN/n-silicon structure show a diode-type characteristic.

Oxidation Resistant Dilute Copper (Boron) Alloy Films Prepared by DC-Magnetron Cosputtering

1996 ◽  
Vol 427 ◽  
Author(s):  
S. Hymes ◽  
K. S. Kumar ◽  
S. P. Murarka ◽  
W. Wang ◽  
W. A. Lanford
Keyword(s):  
Integrated Circuits ◽  
Pure Copper ◽  
Residual Resistivity ◽  
Copper Films ◽  
X Ray Diffraction ◽  
Alloy Films ◽  
Oxidation Rates ◽  
Silicon Integrated Circuits ◽  
Oxidation Resistant ◽  
The Common

AbstractTo enhance the corrosion resistance and reliability of the proposed copper interconnections in silicon integrated circuits, alloying with small amounts thermodynamically favorable elements has been pursued. In the present investigation dilute copper (boron) alloy thin films (in boron concentration range of 0-4 at % in copper) were deposited by DC magnetron co-sputtering using a high purity copper and Cu-4 at % B targets. Films were then annealed in Ar-3% H2, pure Ar, vacuum, and air ambients in the temperature range of 200–500°C. Sheet resistance, Rutherford backscattering, x-ray diffraction measurements were made to characterize the films. The residual resistivity of the as-deposited alloy films was found to be 5.3 μΩ-cm/at %. To obtain sufficiently low working resistivity, an alloy content below 0.5 at % is suggested for application as a potential “metallization material. The addition of boron, which is the common dopant in Si, to the copper films offers considerable oxidation protection. The resulting oxidation rates are considerably lower than that for pure copper films. All this will be presented and discussed.

Oxidation Resistant Dilute Copper (Boron) Alloy Films Prepared by DC-Magnetron Cosputtering

1996 ◽  
Vol 428 ◽  
Author(s):  
S. Hymes ◽  
K. S. Kumar ◽  
S. P. Murarka ◽  
W. Wang ◽  
W. A. Lanford
Keyword(s):  
Integrated Circuits ◽  
Pure Copper ◽  
Residual Resistivity ◽  
Copper Films ◽  
X Ray Diffraction ◽  
Alloy Films ◽  
Oxidation Rates ◽  
Silicon Integrated Circuits ◽  
Oxidation Resistant ◽  
The Common

AbstractTo enhance the corrosion resistance and reliability of the proposed copper interconnections in silicon integrated circuits, alloying with small amounts thermodynamically favorable elements has been pursued. In the present investigation dilute copper (boron) alloy thin films (in boron concentration range of 0–4 at % in copper) were deposited by DC magnetron co-sputtering using a high purity copper and Cu-4 at. % B targets. Films were then annealed in Ar-3% H2, pure Ar, vacuum, and air ambients in the temperature range of 200–500°C. Sheet resistance, Rutherford backscattering, x-ray diffraction measurements were made to characterize the films. The residual resistivity of the as-deposited alloy films was found to be 5.3 μΩ-cm/at %. To obtain sufficiently low working resistivity, an alloy content below 0.5 at % is suggested for application as a potential metallization material. The addition of boron, which is the common dopant in Si. to the copper films offers considerable oxidation protection. The resulting oxidation rates are considerably lower than that for pure copper films. All this will be presented and discussed.

POST‐METALLIZATION ANNEALING OF ULTRA‐THIN REMOTE PLASMA ENHANCED CVD OXIDES

1996 ◽  
Vol 446 ◽  
Author(s):  
L‐Å Ragnarsson ◽  
P. Lundgren ◽  
D. Landheer
Keyword(s):  
Vapour Deposition ◽  
Chemical Vapour ◽  
Interface State ◽  
State Density ◽  
Silicon Substrates ◽  
Constant Voltage ◽  
Remote Plasma ◽  
Current Voltage ◽  
Voltage Stress ◽  
Capacitance Voltage

AbstractA remote plasma enhanced chemical vapour deposition (RPECVD) process was used to deposit thin silicon dioxides on silicon substrates. The oxide properties were compared with thermal oxides with similar thicknesses (2.5–9 nm) using capacitance‐voltage (C‐V), current‐voltage (I‐V) and constant voltage stress measurements (I‐t). Post‐metallization annealing (PMA) showed different annealing dynamics as compared to the thermal oxides for anneal times below approximately 1000 s (at 260 °C) after which the dynamics were similar. The deposited oxides had a higher initial interface state density (Dit) than the thermal oxides, but after PMA they were found to be of the same quality as the thermal oxides. Positive charging of the deposited oxides during constant voltage stress was the same as for thermal oxides, showing that the stress endurance of the two are similar.

scholarly journals Коррелированное изменение электрических характеристик тонкопленочного полевого транзистора при модификации физических свойств его оксидного полупроводникового канала (InZnO : N)

2018 ◽  
Vol 44 (20) ◽  
pp. 95
Author(s):  
А.Б. Черемисин ◽  
Н.А. Кулдин
Keyword(s):  
Field Effect Transistor ◽  
Oxide Semiconductor ◽  
Charge Accumulation ◽  
Electrical Parameters ◽  
Oxide Semiconductors ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Current Voltage Characteristics ◽  
Effect Transistor ◽  
Photoinduced Charge

AbstractWe have studied changes in the transmission and current–voltage characteristics of a thin-film field-effect transistor (TFT) during modification of the physical properties of its oxide semiconductor channel based on InZnO:N layer. Modification of the electrical parameters of the device was based on the phenomenon of photoinduced charge accumulation in the semiconductor. It is established that the slopes and intercepts of the capacitance–voltage ( C _G– V _G) and transmission ( I _D– V _G) curves of the TFT under illumination exhibit correlated similar variations. The obtained results justify joint use of the C _G– V _G and I _D– V _G curves in the analysis of peculiarities of the energy band structure of oxide semiconductors.

scholarly journals Role of interfacial layer thickness on high-κ dielectric-based MOS devices

2014 ◽  
Vol 04 (03) ◽  
pp. 1450023 ◽  
Author(s):  
C. Chakraborty
Keyword(s):  
Interfacial Layer ◽  
Oxide Semiconductor ◽  
Mos Devices ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Current Change ◽  
Higher Temperature ◽  
Lower Temperature ◽  
Substrate Temperatures

An attempt has been made to investigate the role of interfacial layer (IL) and its thickness on HfO 2-based high-κ metal-oxide-semiconductor (MOS) devices. The capacitance–voltage (C–V) and current–voltage (I–V) characteristics have been simulated using Sentaurus TCAD software for two different IL thicknesses and at different substrate temperatures and doping concentrations. The device performance is found to be improved for an IL thickness of 1 nm at higher temperature but deteriorates with further increase in IL thickness. The capacitance value decreases with the increase in IL thickness and a flatband voltage shift (V fb ) due to the presence of interfacial charges at IL of higher thickness is observed. The analysis of I–V curve further shows that the leakage current change is more prominent at lower temperature for different IL thickness. The temperature dependence C–V curves show that the presence of 1 nm IL makes the device more reliable at elevated temperature.

Laser Engineering of Barrier Structures Based on Solid Solution ZnCdHgTe.

2002 ◽  
Vol 719 ◽  
Author(s):  
Galina Khlyap
Keyword(s):  
Room Temperature ◽  
Film Surface ◽  
Charge Carriers ◽  
Barrier Structure ◽  
Free Charge ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Laser Engineering ◽  
Charged Defects ◽  
Epilayer Surface

AbstractRoom-temperature electric investigations carried out in CO2-laser irradiated ZnCdHgTe epifilms revealed current-voltage and capacitance-voltage dependencies typical for the metal-semiconductor barrier structure. The epilayer surface studies had demonstrated that the cell-like relief has replaced the initial tessellated structure observed on the as-grown samples. The detailed numerical analysis of the experimental measurements and morphological investigations of the film surface showed that the boundaries of the cells formed under the laser irradiation are appeared as the regions of accumulation of derived charged defects of different type of conductivity supplying free charge carriers under the applied electric field.

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