The Benefits of Process Parameter Ramping During The Plasma Etching of High Aspect Ratio Silicon Structures

1998 ◽  
Vol 546 ◽  
Author(s):  
J. Hopkins ◽  
H. Ashraf ◽  
J. K. Bhardwaj ◽  
A. M. Hynes ◽  
I. Johnston ◽  
...  

AbstractIn the ongoing enhancement of MEMS applications, the STS Advanced Silicon Etch, (ASETM). process satisfies the demanding requirements of the industry. Typically, highly anisotropic. high aspect ratios profiles with fine CD (critical dimension) control are required. Selectivities to photoresist of 150:1 with Si etch rates of up to 10μm/min are demonstrated. Applications range from shallow etched optical devices to through wafer membrane etches. This paper details some of the fundamental trends of the ASETM process and goes on to discuss how the process has been enhanced to meet product specifications. Parameter ramping is a powerful technique used to achieve the often-conflicting requirements of high etch rate with good profile/CD control. The results are presented in this paper.

Materials ◽  
2021 ◽  
Vol 14 (2) ◽  
pp. 380
Author(s):  
Jun-Hyun Kim ◽  
Sanghyun You ◽  
Chang-Koo Kim

Si surfaces were texturized with periodically arrayed oblique nanopillars using slanted plasma etching, and their optical reflectance was measured. The weighted mean reflectance (Rw) of the nanopillar-arrayed Si substrate decreased monotonically with increasing angles of the nanopillars. This may have resulted from the increase in the aspect ratio of the trenches between the nanopillars at oblique angles due to the shadowing effect. When the aspect ratios of the trenches between the nanopillars at 0° (vertical) and 40° (oblique) were equal, the Rw of the Si substrates arrayed with nanopillars at 40° was lower than that at 0°. This study suggests that surface texturing of Si with oblique nanopillars reduces light reflection compared to using a conventional array of vertical nanopillars.


Author(s):  
Marie Pinti ◽  
Shaurya Prakash

Hybrid microfluidic and nanofluidic devices have a variety of applications including water desalination, molecular gates and DNA sieving among several other lab-on-chip uses. Most microfluidic and nanofluidic devices currently are fabricated in glass, silicon, polydimethylsiloxane (PDMS), or with a combination of these materials. In order to impart functionality, metals, polymers or auxiliary components are often integrated with these devices. Ultra-low aspect ratio channels have several advantages including critical dimensions on the nanoscale but increased throughput compared to higher aspect ratio channels with the same critical dimension, which is important for applications where a higher volumetric flow rate is desired. Additionally, theoretical analysis is significantly easier as ultra-low aspect ratio channels can be modeled as 1-D systems. The fabrication methods for achieving low aspect ratios (< 0.005) usually require extensive facilities with several innovative fabrication and bonding schemes being previously reported. In this paper, we report on fabrication and bonding of ultra-low aspect ratio microfluidic and nanofluidic devices with aspect ratios at 0.0005 in glass/PDMS devices in contrast to the previous best reported result of 0.005 achieved in a silica device using stamp and stick PDMS bonding. The simplicity of our approach presents a new pathway to achieving the lowest aspect ratio nanochannels ever reported for channels fabricated using an interfacial layer for bonding. Centimeter long nanochannels on a borosilicate substrate were fabricated by standard UV photolithography followed by wet etching. Surface roughness of the fabricated channels is on the same order as the roughness of the initial substrate (2–3 nm) and therefore can enable fabrication of channels with critical dimensions approaching 15 nm or less. Devices were then bonded using a second borosilicate substrate with a thin PDMS adhesion layer (∼ 2 μm). The PDMS adhesion layer allows rapid, facile, and alignment-free bonding compared to traditional fusion or anodic bonds. Successful verification of device operation and functionality was determined by verifying flow in operational devices and with scanning electron microscopy to confirm bonding for the formation of nanochannels.


2013 ◽  
Vol 740-742 ◽  
pp. 825-828 ◽  
Author(s):  
Jerome Biscarrat ◽  
Jean François Michaud ◽  
Emmanuel Collard ◽  
Daniel Alquier

Due to its inert chemical nature, plasma etching is the most effective technique to pattern SiC. In this paper, dry etching of 4H-SiC substrate in Inductively Coupled Plasma (ICP) has been studied in order to evaluate the impact of process parameters on the characteristics of etching such as etch rate and trenching effect. Key process parameters such as platen power and ICP coil power prove to be essential to control the SiC etch rate. On the other hand, the ICP coil power and the working pressure mainly master the trenching effect. Our results enlighten that high etch rate with minimal trenching effect can be obtained using high ICP coil power and low working pressure.


2008 ◽  
Vol 1108 ◽  
Author(s):  
Xiaoyan Xu ◽  
Vladimir Kuryatkov ◽  
Boris Borisov ◽  
Mahesh Pandikunta ◽  
Sergey A Nikishin ◽  
...  

AbstractThe effect of BCl3 and BCl3/Ar pretreatment on Cl2/Ar and Cl2/Ar/BCl3 dry etching of AlN is investigated using inductively coupled plasma reactive ion etching. The native AlN oxide can be effectively removed by a short exposure to BCl3 or BCl3/Ar plasma. Compared to the chlorine based plasma etching, BCl3/Ar is found to have the highest etch rate for both AlN and its native oxide. Following removal of the native oxide, Cl2/Ar/BCl3 plasma etching with 15% BCl3 fraction results in a high etch rate ˜ 87 nm/min and modest increases in the surface roughness.


1990 ◽  
Vol 29 (Part 1, No. 11) ◽  
pp. 2641-2643 ◽  
Author(s):  
Haruo Shindo ◽  
Tetsuro Hashimoto ◽  
Fumitake Amasaki ◽  
Yasuhiro Horiike

2012 ◽  
Vol 711 ◽  
pp. 66-69 ◽  
Author(s):  
Ji Hoon Choi ◽  
Laurence Latu-Romain ◽  
Florian Dhalluin ◽  
Thierry Chevolleau ◽  
Bassem Salem ◽  
...  

A top-down fabrication technique for nanometer scale silicon carbide (SiC) pillars has been demonstrated by using inductively coupled SF6/O2 plasma etching. At optimal etching conditions, the obtained SiC nanopillars exhibit high anisotropy features (aspect ratio ~ 6.5) with high etch depth (>7 μm). The etch characteristics of SiC nanopillars under these conditions show a high etch rate (550 nm/min) and a high selectivity (over 60 for Ni).


Author(s):  
Leslie M. Phinney ◽  
Bonnie B. McKenzie ◽  
James A. Ohlhausen ◽  
Thomas E. Buchheit ◽  
Randy J. Shul

Deep reactive ion etching (DRIE) of silicon enables high aspect ratio, deep silicon features that can be incorporated into the fabrication of microelectromechanical systems (MEMS) sensors and actuators. The DRIE process creates silicon structures and consists of three steps: conformal polymer deposition, ion sputtering, and chemical etching. The sequential three step process results in sidewalls with roughness that varies with processing conditions. This paper reports the sidewall roughness for DRIE etched MEMS as a function of trench width from 5 μm to 500 μm for a 125 μm thick device layer corresponding to aspect ratios from 25 to 0.25. Using a scanning electron microscope (SEM), the surfaces were imaged detecting an upper region exhibiting a scalloping morphology and a rougher lower region exhibiting a curtaining morphology. The height of rougher curtaining region increases linearly with aspect ratio when the etch cleared the entire device layer. The surface roughness for two trench widths: 15 μm and 100 μm were further characterized using an atomic force microscope (AFM), and RMS roughness values are reported as a function of height along the surface. The sidewall roughness varies with height and depends on the trench width.


1998 ◽  
Author(s):  
Tam Pandhumsoporn ◽  
Lei Wang ◽  
Michael Feldbaum ◽  
Prashant Gadgil ◽  
Michel Puech ◽  
...  

2021 ◽  
Author(s):  
Yu-Chih Chen ◽  
Bing-Chang Li ◽  
Pei-Ling Hsu ◽  
Tsung-Yi Lin ◽  
I-An Chen ◽  
...  

Abstract The 3D NAND sample with high aspect ratio (HAR) etched by plasma was investigated. By controlling the plasma etching parameters, a relatively high etch rate could be obtained. Moreover, with appropriately controlling the etch time, we could etch top region of HAR sample with expected number of layers, which could help us to completely analyze the high aspect ratio sample with TEM cross-section analysis, especially for the middle region of 3D NAND.


2007 ◽  
Vol 1020 ◽  
Author(s):  
Yoshinori Matsui ◽  
Nozomi Miyoshi ◽  
Akihiro Oshima ◽  
Shu Seki ◽  
Masakazu Washio ◽  
...  

AbstractPoly(tetrafluoroethylene) (PTFE) microstructure with high aspect ratio (> 200) and without solid debris along the edge was fabricated with high etch rate by using FIB. Gasification of PTFE by FIB is responsible for the high aspect ratio, the high etch rate, and the no solid debris. Roughness of etched surface of the PTFE increases with fluence, although edge of the etched area has good profiles. The etch mechanism seems to be complicated.


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