scholarly journals Low Leakage Approximate multiplier design for high Performance Error Tolerant Applications

2021 ◽  
Vol 58 (2) ◽  
pp. 5657-5661
Author(s):  
Supratim Saha, Dr. Amit Kumar Jain
Keyword(s):  
Circuit Design ◽  
Calculation Method ◽  
Power Dissipation ◽  
High Performance ◽  
Fault Tolerant ◽  
Leakage Power ◽  
Vlsi Circuit ◽  
Control Techniques ◽  
Low Leakage ◽  
Performance Error

Power dissipation has become a major concern in VLSI circuit design with the rapid launch of battery powered applications. In high-performance constructions, the leakage component of power consumption is comparable to the switching component. This percentage increases as the technology scales unless effective leak control techniques are in place. In the case of fault-tolerant applications it is also not necessary to adhere to the exact calculation method. Therefore, an approximate multiplier of 8 x 8 is developed in this article using several proposed techniques to reduce leakage power such as MTCMOS, DUAL-Vt, and LECTOR. All of the above techniques are simulated with a tanning tool using 90 nm technology.

High performance low leakage power full adder circuit design using rate sensing keeper

2014 ◽  
Author(s):  
J. Ajayan ◽  
D. Nirmal ◽  
D. Sivaranjani ◽  
S. Sivasankari ◽  
M. Manikandan
Keyword(s):  
Circuit Design ◽  
High Performance ◽  
Full Adder ◽  
Leakage Power ◽  
Low Leakage

Various Logically Optimized D Flip Flop Circuits-A Comparative Study in Submicron Technology

2015 ◽  
Vol 4 (2) ◽  
Author(s):  
Abhijit Asthana ◽  
Shyam Akashe
Keyword(s):  
Comparative Study ◽  
Power Dissipation ◽  
Leakage Power ◽  
Simulation Test ◽  
Flip Flop ◽  
Chip Area ◽  
Low Leakage ◽  
Signal Systems ◽  
To Come ◽  
Power Delay Product

D-Flip Flop (D_FF) is a very important component of various digital, analog and mixed signal systems and designs. It is obvious to come up with optimized D_FF, that cater the needs of low leakage power, less power dissipation, less chip area on the chip and low delays. This paper presents a comparative study of various logically optimized circuits of D_FF using 8T, 11T, 12T and conventional 18T D_FF. The simulation, test circuits, schematics & layouts etc are done on Cadence Virtuoso tool in 180 nm technology. Designs are compared on grounds of power dissipation, leakage power, delays and power delay product.

High-performance digital VLSI circuit design

1997 ◽  
Vol 28 (2) ◽  
pp. 201
Author(s):  
S.L. Hurst
Keyword(s):  
Circuit Design ◽  
High Performance ◽  
Vlsi Circuit ◽  
Digital Vlsi

scholarly journals Estimation of Leakage Power and Delay in CMOS Circuits

2020 ◽  
Vol 4 (7) ◽  
pp. 14-19
Author(s):  
Mohasinul Huq N Md ◽  
Mohan Das S ◽  
Bilal N Md
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Full Adder ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Leakage Power ◽  
Nand Gate ◽  
High Threshold ◽  
Cmos Circuits ◽  
Low Leakage

This paper presents an estimation of leakage power and delay for 1-bit Full Adder (FA)designed which is based on Leakage Control Transistor (LCT) NAND gates as basic building block. The main objective is to design low leakage full adder circuit with the help of low and high threshold transistors. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. The saving in leakage power dissipation for LCT NAND_HVT gate is up to 72.33% and 45.64% when compared to basic NAND and LCT NAND gate. Similarly for 1-bit full adder the saving is up to 90.9% and 40.08% when compared to basic NAND FA and LCT NAND.

High-Performance Digital VLSI Circuit Design

1996 ◽  
Author(s):  
Richard X. Gu ◽  
Khaled M. Sharaf ◽  
Mohamed I. Elmasry
Keyword(s):  
Circuit Design ◽  
High Performance ◽  
Vlsi Circuit ◽  
Digital Vlsi

scholarly journals High-Performance and Energy-Efficient Fault Tolerance FPGA-to-FPGA Communication

2021 ◽  
Author(s):  
Naresh Kumar Reddy ◽  
Swamy Cherukuru ◽  
Veena Vani ◽  
Vishal Reddy
Keyword(s):  
Error Detection ◽  
High Speed ◽  
High Performance ◽  
Fault Tolerant ◽  
Key Factors ◽  
Error Detection And Correction ◽  
Performance Error ◽  
Increasing Demand ◽  
Accuracy Performance ◽  
Or Applications

Abstract These days, due to the increasing demand for high speed and parallel computation, several real world applications and systems include multiple FPGAs in them. Due to this, FPGAs often need to communicate among them. So, communication between the FPGAs is one of the key factors that determines the accuracy, performance and correctness of the entire multiple FPGAs systems or applications. This paper presents the design of an efficient multi-bit fault tolerant communication system for FPGA-to-FPGA communication. The proposed design is synthesized and also simulated through Vivado design suit 2018.3 and was communicated with two Kintex-7 FPGA boards. When compared with the existing FPGA-to-FPGA communication and inter FPGA communication designs, the proposed design have higher performance, error detection and correction capability.

scholarly journals Ultra-Low-Leakage and High-Performance Logic Circuit Design Using Multiparameter Asymmetric FinFETs

2016 ◽  
Vol 12 (4) ◽  
pp. 1-25 ◽  
Author(s):  
Sourindra M. Chaudhuri ◽  
Niraj K. Jha
Keyword(s):  
Circuit Design ◽  
High Performance ◽  
Logic Circuit ◽  
Low Leakage
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