Comparative Analysis of Flip-Flops and Application of Data-Gating in Dynamic Flip-Flops for High Speed, Low Active and Low Leakage Power Dissipation

2002 ◽  
pp. 3-17
Author(s):  
Vamsi Srikantam ◽  
Mario Martinez
Keyword(s):  
Comparative Analysis ◽  
Power Dissipation ◽  
High Speed ◽  
Leakage Power ◽  
Low Leakage ◽  
Leakage Power Dissipation

CNTFET Circuit-Based Wide Fan-In Domino Logic for Low Power Applications

2021 ◽  
pp. 2250036
Author(s):  
Vijay Kumar Sharma
Keyword(s):  
Power Dissipation ◽  
Field Effect ◽  
Performance Metrics ◽  
Field Effect Transistors ◽  
High Current Density ◽  
Cylindrical Tube ◽  
Leakage Power ◽  
Oxide Semiconductor ◽  
Domino Logic ◽  
Leakage Power Dissipation

Carbon nanotube field effect transistors (CNTFETs) are the best alternative option for the metal oxide semiconductor field effect transistor (MOSFET) in the ultra-deep submicron (ultra-DSM) regime. CNTFET has numerous benefits such as lower off-state current, high current density, low bias potential and better transport property as compared to MOSFET. A rolled graphene sheet-based cylindrical tube is constructed in the channel region of the CNTFET structure. In this paper, an improved domino logic (IDL) configuration is proposed for domino logic circuits to improve the different performance metrics. An extensive comparative simulation analysis is provided for the different performance metrics for different circuits to verify the novelty of the proposed IDL approach. The IDL approach saves the leakage power dissipation by 95.61% and enhances the speed by 87.10% for the 4-bit full adder circuit as compared to the best reported available domino method. The effects of the number of carbon nanotubes (CNTs), temperature, and power supply voltage variations are estimated for leakage power dissipation for the 16-input OR (OR16) gate. The reliability of different performance metrics for different circuit is calculated in terms of uncertainty by running the Monte Carlo simulations for 500 samples. Stanford University’s 32[Formula: see text]nm CNTFET model is applied for circuit simulations.

Various Logically Optimized D Flip Flop Circuits-A Comparative Study in Submicron Technology

2015 ◽  
Vol 4 (2) ◽  
Author(s):  
Abhijit Asthana ◽  
Shyam Akashe
Keyword(s):  
Comparative Study ◽  
Power Dissipation ◽  
Leakage Power ◽  
Simulation Test ◽  
Flip Flop ◽  
Chip Area ◽  
Low Leakage ◽  
Signal Systems ◽  
To Come ◽  
Power Delay Product

D-Flip Flop (D_FF) is a very important component of various digital, analog and mixed signal systems and designs. It is obvious to come up with optimized D_FF, that cater the needs of low leakage power, less power dissipation, less chip area on the chip and low delays. This paper presents a comparative study of various logically optimized circuits of D_FF using 8T, 11T, 12T and conventional 18T D_FF. The simulation, test circuits, schematics & layouts etc are done on Cadence Virtuoso tool in 180 nm technology. Designs are compared on grounds of power dissipation, leakage power, delays and power delay product.

scholarly journals Estimation of Leakage Power and Delay in CMOS Circuits

2020 ◽  
Vol 4 (7) ◽  
pp. 14-19
Author(s):  
Mohasinul Huq N Md ◽  
Mohan Das S ◽  
Bilal N Md
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Full Adder ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Leakage Power ◽  
Nand Gate ◽  
High Threshold ◽  
Cmos Circuits ◽  
Low Leakage

This paper presents an estimation of leakage power and delay for 1-bit Full Adder (FA)designed which is based on Leakage Control Transistor (LCT) NAND gates as basic building block. The main objective is to design low leakage full adder circuit with the help of low and high threshold transistors. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. The saving in leakage power dissipation for LCT NAND_HVT gate is up to 72.33% and 45.64% when compared to basic NAND and LCT NAND gate. Similarly for 1-bit full adder the saving is up to 90.9% and 40.08% when compared to basic NAND FA and LCT NAND.

A New Keeper Domino Logic Based Full Adder for High Speed Arithmetic Circuits

2020 ◽  
Vol 12 ◽  
Author(s):  
Deepika Bansal ◽  
Bal Chand Nagar ◽  
Ajay Kumar ◽  
Brahamdeo Prasad Singh
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
High Efficiency ◽  
Dynamic Logic ◽  
Full Adder ◽  
Leakage Power ◽  
Low Leakage ◽  
Dynamic Circuits ◽  
Power Delay Product ◽  
Domino Circuits

Objective: A new efficient keeper circuit has been proposed in this article for achieving low leakage power consumption and to improve power delay product of the dynamic logic using carbon nanotube MOSFET. Method: As a benchmark, an one-bit adder has been designed and characterized with both technologies Si-MOSFET and CN-MOSFET using proposed and existing dynamic circuits. Furthermore, a comparison has been made to demonstrate the superiority of CN-MOSFET technology with Synopsys HSPICE tool for multiple bit adders available in the literature. Result: The simulation results show that the proposed keeper circuit provides lower static and dynamic power consumption up to 57 and 40% respectively, as compared to the domino circuits using 32nm CN-MOSFET technology provided by Stanford University. Moreover, the proposed keeper configuration provides better performance using SiMOSFET and CN-MOSFET technologies. Conclusion: A comparison of the proposed keeper with previously published designs is also given in terms of power consumption, delay and power delay product with the improvement up to 75, 18 and 50% respectively. The proposed circuit uses only two transistors, so it requires less area and gives high efficiency.

TECHNIQUES FOR LOW LEAKAGE NANOSCALE VLSI CIRCUITS: A COMPARATIVE STUDY

2014 ◽  
Vol 23 (05) ◽  
pp. 1450061 ◽  
Author(s):  
VIJAY KUMAR SHARMA ◽  
MANISHA PATTANAIK
Keyword(s):  
Threshold Voltage ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Deep Submicron ◽  
Leakage Power ◽  
Vlsi Circuits ◽  
Oxide Semiconductor ◽  
Leakage Reduction ◽  
Reduction Techniques ◽  
Leakage Power Dissipation

Since the last two decades, the trend of device miniaturization has increased to get better performance with a smaller area of the logic functions. In deep submicron regime, the demand of fabrication of nanoscale Complementary metal oxide semiconductor (CMOS) VLSI circuits has increased due to evaluation of modern successful portable systems. Leakage power dissipation and reliability issues are major concerns in deep submicron regime for VLSI chip designers. Power supply voltage has been scaled down to maintain the performance yield in future deep submicron regime. The threshold voltage is the critical parameter to trade-off the performance yield and leakage power dissipation in nanoscaled devices. Low threshold voltage improves the device characteristics with large leakage power in nanoscaled devices. Several leakage reduction techniques at different levels are used to mitigate the leakage power dissipation. Lower leakage power increases the reliability by reducing the cooling cost of the portable systems. In this article, we are presenting the explanatory general review of the commonly used leakage reduction techniques at circuit level. We have analyzed the NAND3 gate using HSPICE EDA tool for leakage power dissipation at different technology nodes in active as well as standby modes. Process, voltage and temperature effects are checked for reliability purpose. Our comparative results and discussion of different leakage reduction techniques are very useful to illustrate the effective technique in active and standby modes.

Low Leakage Optimization Techniques for Multi-threshold CMOS Circuits

2020 ◽  
Vol 10 (5) ◽  
pp. 696-708
Author(s):  
Rumi Rastogi ◽  
Sujata Pandey ◽  
Mridula Gupta
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
High Speed ◽  
Room Temperature ◽  
Leakage Power ◽  
Optimization Techniques ◽  
Power Gating ◽  
Low Leakage ◽  
Charge Recycling ◽  
A New Technique

Background: With the reducing size of the devices, the leakage power has also increased exponentially in the nano-scale CMOS devices. Several techniques have been devised so far to minimize the leakage power, among which, MTCMOS (power-gating) is the preferred one as it effectively minimizes the leakage power without any complexity in the circuit. However, the power-gating technique suffers from problems like transition noise and delay. In this paper, we proposed a new simple yet effective technique to minimize leakage power in MTCMOS circuits. Objective: The objective of the paper was to propose a new technique which effectively minimizes leakage power in nanoscale power-gated circuits with minimal delay, noise and area requirement so that it can well be implemented in high-speed low-power digital integrated circuits. Methods: A new power-gating structure has been proposed in this paper. The new proposed technique includes three parallel NMOS transistors with variable widths which are functional during the active mode to reduce the on-time delay. A PMOS footer with gate-bias is also connected in parallel with the NMOS footer transistors. The proposed technique has been verified through simulation in 45nm MTCMOS technology to implement a 32 bit adder circuit. Results: The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation energy. The technique reduced the leakage power effectively at room temperature as well as higher temperatures. The reactivation noise produced by the proposed technique minimized by 98.7%, 64.8%, 62.07% and 24.47% as compared to the parallel transistor, variable-width, charge-recycling and the modified-charge recycling techniques respectively at room temperature.The reactivation energy of the proposed technique also minimized by 77.by 77.67%, 55.8%, 45.1%, and 18.32% with respect to the parallel transistor, variable-width, CR and Modified-CR techniques, respectively. Conclusion: The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation energy. The technique reduces the leakage power effectively at room temperature as well as at higher temperatures. Since the delay and area overhead of the proposed structure is minimal, hence it can be easily implemented in high-speed low-power digital circuits.

scholarly journals Consequences of Body-Biasing Technique on SRAM Memory

2019 ◽  
Vol 8 (10) ◽  
pp. 2922-2925
Keyword(s):  
Threshold Voltage ◽  
High Speed ◽  
Supply Voltage ◽  
Tunneling Current ◽  
Memory Device ◽  
Leakage Power ◽  
The Body ◽  
Low Leakage ◽  
Body Biasing ◽  
Body Bias

The circuit changes the threshold voltage effectively with a definite delay and power by altering the body biasing of the transistors. The body bias is employed to govern the frequency and leakage of the memory device. The threshold voltage of individual transistor is decreases by applying the reverse body bias (RBB) and increases with forward body bias (FBB). This paper presents the viability of RBB to decrease the leakage power and increase in the speed of operations for SRAM circuit. The investigation of RBB dependencies on various performance parameters are analyzed. It is observed that the leakage power improves by 30.32% on applying RBB voltage compared to zero body bias while the transient power increases by 3.22% but decrease of delay by 84.56% dominates on it. Because of this the overall energy consumption reduces by 84.06%. Further the simulation work is carried out to see effect of supply voltage variation on leakage power at different RBB voltage and temperature. Therefore, the RBB scheme is beneficial for devices of low leakage, low energy and high speed of operation but this RBB voltage is limited by band-to-band tunneling current.

A Novel Low Power Technique for FinFET Domino OR Logic

2020 ◽  
pp. 2150117
Author(s):  
Kajal ◽  
Vijay Kumar Sharma
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Large Scale ◽  
Logic Gates ◽  
Leakage Power ◽  
Oxide Semiconductor ◽  
Domino Logic ◽  
Large Power ◽  
Leakage Reduction ◽  
The Impact

Excessive scaling of complementary metal oxide semiconductor (CMOS) technology is the main reason of large power dissipation in electronic circuits. Very large-scale integration (VLSI) industry has chosen an alternative option known as fin-shaped field effect transistor (FinFET) technology to mitigate the large power dissipation. FinFET is a multi-gate transistor which dissipates less leakage power as compared to CMOS transistors, but it does not completely resolve the problem of power dissipation. So, leakage reduction approaches are always required to mitigate the impact of power dissipation. In this paper, cascaded leakage control transistors (CLCT) leakage reduction technique is proposed using FinFET transistors. CLCT approach is tested for basic static logic circuits like inverter, 2-input NAND and NOR gates and compared with the existing leakage reduction techniques for leakage power dissipation and delay calculations at 16 and 14 nm technology nodes using Cadence tools. CLCT approach shows the effective reduction of leakage power with minimum delay penalty. As the domino logic gates are widely used in large memories and high-speed processors therefore, CLCT approach is further utilized for footless domino logic (FLDL) and compared with the available methods at 14[Formula: see text]nm technology node. CLCT approach reduces 35.16% power dissipation as compared to the conventional domino OR logic. Temperature and multiple parallel fin variations are estimated for the domino OR logic to check its reliable operation. CLCT approach has high-noise tolerance capability in term of unity noise gain (UNG) for domino OR logic as compared to the other methods.

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