scholarly journals The Mixed Current Model of Nano-MOSFETs Considering the Effect of Horizontal and Vertical Electric Fields

2019 ◽  
Author(s):  
Heng-Sheng Huang ◽  
Ping-Ray Huang ◽  
Mu-Chun Wang ◽  
Shuang-Yuan Chen ◽  
Shea-Jue Wang ◽  
...  
Keyword(s):  
Electric Fields ◽  
Current Model ◽  
Atomic Layer ◽  
Diffusion Current ◽  
Electrical Performance ◽  
Short Channel ◽  
Drive Current ◽  
Layer Deposition ◽  
And Diffusion ◽  
Better Than

A novel drive current model covering the effects of source/drain voltage (VDS) and gate voltage (VGS) and incorporating drift and diffusion current on the surface channel at the nano-node level, especially beyond 28nm node is presented. The effect of the diffusion current added is more satisfactory to describe the behavior of the drive current in nano-node MOSFETs, fabricated with the atomic-layer-deposition (ALD) technology. This breakthrough in model establishment can expose the long and short channel devices together. Introducing the variables of VDS and VGS, the mixed current model more effectively and meaningfully demonstrates the drive current of MOSFETs under the operation of horizontal, vertical, or mixed electrical field. In comparison between the simulation and experimental consequences, the electrical performance is impressive. The error between both is less than 1%, better than the empirical adjustment to issue a set of drive current models.

scholarly journals Atomic Layer Deposition (ALD) of Metal Gates for CMOS

2019 ◽  
Vol 9 (11) ◽  
pp. 2388 ◽  
Author(s):  
Chao Zhao ◽  
Jinjuan Xiang
Keyword(s):  
Atomic Layer Deposition ◽  
Field Effect Transistors ◽  
Material Selection ◽  
Atomic Layer ◽  
Oxide Semiconductor ◽  
Metal Gate ◽  
Gate Stack ◽  
Short Channel ◽  
Metal Gates ◽  
Layer Deposition

The continuous down-scaling of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) had been suffering two fateful technical issues, one relative to the thinning of gate dielectric and the other to the aggressive shortening of channel in last 20 years. To solve the first issue, the high-κ dielectric and metal gate technology had been induced to replace the conventional gate stack of silicon dioxide layer and poly-silicon. To suppress the short channel effects, device architecture had changed from planar bulk Si device to fully depleted silicon on insulator (FDSOI) and FinFETs, and will transit to gate all-around FETs (GAA-FETs). Different from the planar devices, the FinFETs and GAA-FETs have a 3D channel. The conventional high-κ/metal gate process using sputtering faces conformality difficulty, and all atomic layer deposition (ALD) of gate stack become necessary. This review covers both scientific and technological parts related to the ALD of metal gates including the concept of effect work function, the material selection, the precursors for the deposition, the threshold voltage (Vt) tuning of the metal gate in contact with HfO2/SiO2/Si. The ALD of n-type metal gate will be detailed systematically, based mainly on the authors’ works in last five years, and the all ALD gate stacks will be proposed for the future generations based on the learning.

scholarly journals A Study on Solution-Processed Y2O3 Films Modified by Atomic Layer Deposition Al2O3 as Dielectrics in ZnO Thin Film Transistor

Coatings ◽  
2021 ◽  
Vol 11 (8) ◽  
pp. 969
Author(s):  
Haiyang Xu ◽  
Xingwei Ding ◽  
Jie Qi ◽  
Xuyong Yang ◽  
Jianhua Zhang
Keyword(s):  
Thin Film ◽  
Atomic Layer Deposition ◽  
Active Layer ◽  
Dielectric Layer ◽  
Thin Film Transistor ◽  
Atomic Layer ◽  
Electrical Performance ◽  
Zno Thin Film ◽  
Threshold Voltage Shift ◽  
Layer Deposition

In this work, Y2O3–Al2O3 dielectrics were prepared and used in ZnO thin film transistor as gate insulators. The Y2O3 film prepared by the sol–gel method has many surface defects, resulting in a high density of interface states with the active layer in TFT, which then leads to poor stability of the devices. We modified it by atomic layer deposition (ALD) technology that deposited a thin Al2O3 film on the surface of a Y2O3 dielectric layer, and finally fabricated a TFT device with ZnO as the active layer by ALD. The electrical performance and bias stability of the ZnO TFT with a Y2O3–Al2O3 laminated dielectric layer were greatly improved, the subthreshold swing was reduced from 147 to 88 mV/decade, the on/off-state current ratio was increased from 4.24 × 106 to 4.16 × 108, and the threshold voltage shift was reduced from 1.4 to 0.7 V after a 5-V gate was is applied for 800 s.

Characteristics of hafnium oxide grown on silicon by atomic-layer deposition using tetrakis(ethylmethylamino)hafnium and water vapor as precursors

2007 ◽  
Vol 22 (7) ◽  
pp. 1899-1906 ◽  
Author(s):  
Yan-Kai Chiou ◽  
Che-Hao Chang ◽  
Tai-Bor Wu
Keyword(s):  
Thin Films ◽  
Atomic Layer Deposition ◽  
Charge Density ◽  
Photoelectron Spectroscopy ◽  
Hafnium Oxide ◽  
Atomic Layer ◽  
Oxide Semiconductor ◽  
Electrical Performance ◽  
Breakdown Field ◽  
Layer Deposition

The growth of HfO2 thin films on a HF-dipped p-Si(100) substrate at 200 °C by atomic-layer deposition (ALD) using Hf[N(C2H5)(CH3)]4 and H2O vapor as precursors is demonstrated. Uniform HfO2 thin films are obtained on a 4-in. silicon wafer, and the energy-band gap and band offset are determined by x-ray photoelectron spectroscopy analysis. The as-deposited HfO2 thin film is amorphous and able to crystallize at 500 ∼ 600 °C with only the monoclinic phase. As for the electrical performance of Au–Ti–HfO2–Si metal oxide semiconductor capacitors, a dielectric constant of ∼17.8 and an equivalent oxide thickness value of ∼1.39 nm are obtained from the 40-cycle ALD film after annealing at 500 °C. In addition, the breakdown field is in the range of 5 ∼ 5.5 MV/cm, and the fixed charge density is on the order of 1012 cm−2, depending on the annealing temperatures. The interface quality of HfO2 thin films on silicon is satisfactory with an interface-trap charge density of ∼3.7 × 1011 cm−2 eV−1.

scholarly journals Tunneling Atomic Layer-Deposited Aluminum Oxide: a Correlated Structural/Electrical Performance Study for the Surface Passivation of Silicon Junctions

2019 ◽  
Vol 14 (1) ◽  
Author(s):  
Kangping Liu ◽  
Odile Cristini-Robbe ◽  
Omar Ibrahim Elmi ◽  
Shuang Long Wang ◽  
Bin Wei ◽  
...  
Keyword(s):  
Surface Passivation ◽  
Atomic Layer ◽  
Passivation Layer ◽  
Atomic Scale ◽  
Electrical Performance ◽  
Performance Study ◽  
Solar Simulator ◽  
Transmission Electron ◽  
Layer Deposition ◽  
Key Parameter

Abstract Passivation is a key process for the optimization of silicon p-n junctions. Among the different technologies used to passivate the surface and contact interfaces, alumina is widely used. One key parameter is the thickness of the passivation layer that is commonly deposited using atomic layer deposition (ALD) technique. This paper aims at presenting correlated structural/electrical studies for the passivation effect of alumina on Si junctions to obtain optimal thickness of alumina passivation layer. High-resolution transmission electron microscope (HRTEM) observations coupled with energy dispersive X-ray (EDX) measurements are used to determine the thickness of alumina at atomic scale. The correlated electrical parameters are measured with both solar simulator and Sinton’s Suns-Voc measurements. Finally, an optimum alumina thickness of 1.2 nm is thus evidenced.

scholarly journals Harnessing Atomic Layer Deposition and Diffusion to Spatially Localize Rare-Earth Ion Emitters

2020 ◽  
Vol 124 (36) ◽  
pp. 19725-19735
Author(s):  
Alban Ferrier ◽  
Nao Harada ◽  
Marion Scarafagio ◽  
Emrick Briand ◽  
Jean-Jacques Ganem ◽  
...  
Keyword(s):  
Rare Earth ◽  
Atomic Layer Deposition ◽  
Atomic Layer ◽  
Rare Earth Ion ◽  
Layer Deposition ◽  
And Diffusion
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