Air Processed Cs2AgBiBr6 Lead-free Double Perovskite High-mobility Thin Film Field-effect Transistors

Abstract This study focuses on the fabrication and characterization of Cs2AgBiBr6 double perovskite thin film for field-effect transistor (FET) applications. The Cs2AgBiBr6 thin films were fabricated using a solution process technique and the observed XRD patterns demonstrate no diffraction peaks of secondary phases, which confirms the phase-pure crystalline nature. The average grain sizes of the spin-deposited film were also calculated by analysing the statistics of grain size in SEM image and was found to be around 412 (±44) nm the larger grain size was also confirmed by the XRD measurements. FETs with different channel lengths of Cs2AgBiBr6 thin films were fabricated on an electrode deposited heavily doped p-type Si substrate with a 300 nm thermally grown SiO2 dielectric under ideal conditions in air processing under ambient pressure and temperature. The Cs2AgBiBr6 FETs showed a p-type nature with a positive threshold voltage. The on current, threshold voltage and hole-mobility of the FETs decreased with increasing channel length. A high average hole mobility of 0.29 cm2s-1V-1 was obtained for the FETs with a channel length of 30 µm, and the hole mobility was reduced by an order of magnitude (0.012 cm2s-1V-1) when the channel length was doubled. The on current and hole-mobility of Cs2AgBiBr6 FETs followed a power fit, which confirmed the dominance of channel length in electrostatic gating in Cs2AgBiBr6 FETs. A very high-hole mobility observed in or FET that could be attributed to the much larger grain size of Cs2AgBiBr6 film made in this work.

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Optimization of electrical conductivity of SnS thin film of 0.2 < t ≤ 0.4 μm thicknes for field effect transistor application

Revista Mexicana de Física ◽

10.31349/revmexfis.67.263 ◽

2021 ◽

Vol 67 (2 Mar-Apr) ◽

pp. 263

Author(s):

T. O. Daniel ◽

U. E. Uno ◽

K. U. Isah ◽

U. Ahmadu

Keyword(s):

Thin Film ◽

Thin Films ◽

Electrical Conductivity ◽

Grain Size ◽

Grain Boundary ◽

Film Thickness ◽

Threshold Voltage ◽

Field Effect ◽

Field Effect Transistor ◽

Effect Transistor

This study is focused on the investigation of SnS thin film for transistor application. Electron trap which is associated with grain boundary effect affects the electrical conductivity of SnS semiconductor thin film thereby militating the attainment of the threshold voltage required for transistor operation. Grain size and grain boundary is a function of a semiconductor’s thickness. SnS semiconductor thin films of 0.20, 0.25, 0.30, 0.35, 0.40 μm were deposited using aerosol assisted chemical vapour deposition on glass substrates. Profilometry, Scanning electron microscope, Energy dispersive X-ray spectroscopy and hall measurement were used to characterise the composition, microstructure and electrical properties of the SnS thin film. SnS thin films were found to consist of Sn and S elements whose composition varied with increase in thickness. The film conductivity was found to vary with grain size and grain boundary which is a function of the film thickness. The SnS film of 0.4 μm thickness shows optimal grain growth with a grain size of 130.31 nm signifying an optimum for the as deposited SnS films as the larger grains reduces the number of grain boundaries and charge trap density which allows charge carriers to move freely in the lattice thereby causing a reduction in resistivity and increase in conductivity of the films which is essential in obtaining the threshold voltage for a transistor semiconductor channel layer operation. The carrier concentration of due to low resistivity of 3.612 ×105 Ωcm of 0.4 μm SnS thin film thickness is optimum and favours the attainment of the threshold voltage for a field effect transistor operation hence the application of SnS thin film as a semiconductor channel layer in a field effect transistor.

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Vertical Conduction in the New Field Effect Transistors: p-Type and n-Type Vertical Channel Thin Film Transistors

Frontiers in Electronics ◽

10.1142/9789814656917_0010 ◽

2014 ◽

Author(s):

Olivier Bonnaud ◽

Peng Zhang ◽

Emmanuel Jacques ◽

Regis Rogel

Keyword(s):

Thin Film ◽

Thin Film Transistors ◽

Field Effect ◽

Field Effect Transistors ◽

Vertical Channel ◽

P Type

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Diamond Based Field-Effect Transistors of Zr Gate withSiNxDielectric Layers

Journal of Nanomaterials ◽

10.1155/2015/124640 ◽

2015 ◽

Vol 2015 ◽

pp. 1-5 ◽

Cited By ~ 3

Author(s):

W. Wang ◽

C. Hu ◽

S. Y. Li ◽

F. N. Li ◽

Z. C. Liu ◽

...

Keyword(s):

Carrier Density ◽

Field Effect ◽

Field Effect Transistor ◽

Field Effect Transistors ◽

Hole Mobility ◽

Conduction Channel ◽

Effect Transistor ◽

P Type ◽

Interface Bond ◽

Transfer Properties

Investigation of Zr-gate diamond field-effect transistor withSiNxdielectric layers (SD-FET) has been carried out. SD-FET works in normally on depletion mode with p-type channel, whose sheet carrier density and hole mobility are evaluated to be 2.17 × 1013 cm−2and 24.4 cm2·V−1·s−1, respectively. The output and transfer properties indicate the preservation of conduction channel because of theSiNxdielectric layer, which may be explained by the interface bond of C-N. High voltage up to −200 V is applied to the device, and no breakdown is observed. For comparison, another traditional surface channel FET (SC-FET) is also fabricated.

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Properties of CuInS2 Thin Films Fabricated by SEL Method

Solar Energy ◽

10.1115/isec2005-76047 ◽

2005 ◽

Author(s):

Gye-Choon Park ◽

Woon-Jo Jeong ◽

Hyeon-Hun Yang ◽

Hae-Duck Jung ◽

Jin Lee ◽

...

Keyword(s):

Thin Film ◽

Thin Films ◽

Grain Size ◽

Lattice Constant ◽

Energy Band ◽

Optical Energy ◽

Glass Substrates ◽

Cuins2 Thin Films ◽

Sulfur Atmosphere ◽

P Type

CuInS2 thin films were fabricated by sulphurization of S/In/Cu Stacked elemental layers (SEL) on slide glass substrates by annealing in vacuum of 10−3 Torr at temperature of 50 °C ∼ 350 °C. Some S/In/Cu SEL were vacuum annealed under a sulfur atmosphere. The thin films thus annealed were analyzed by measuring structural, electrical and optical properties. When CuInS2 thin films were made under a sulfur atmosphere, lattice constant of a and grain size of the thin film were a little larger than those in only vacuum annealing. The largest lattice constant of a and grain size was 5.63 Å and 1.2 μm respectively. Also, when the thin films were made under a sulfur atmosphere, conduction types were all p-type with resistivities of around 10−1 Ωcm and optical energy band gaps of the films were a little larger than those in only vacuum and the largest optical energy band gap of CuInS2 thin film was 1.53 eV.

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A One-Micrometer Channel Length α-Si Thin-Film Field-Effect Transistor

MRS Proceedings ◽

10.1557/proc-33-293 ◽

1984 ◽

Vol 33 ◽

Cited By ~ 7

Author(s):

Z. Yaniv ◽

G. Hansell ◽

M. Vijan ◽

V. Cannella

Keyword(s):

Thin Film ◽

Field Effect ◽

Field Effect Transistors ◽

Liquid Crystal Displays ◽

Channel Length ◽

Large Area ◽

Short Channel ◽

Threshold Voltages ◽

Effect Transistor ◽

Si Thin Film

ABSTRACTA new method of fabricating short channel α-Si TFTs has been developed. One-micrometer channel length α-Si thin-film field effect transistors have been fabricated and tested. Threshold voltages as low as 1.9V and field-effect mobilities as high as 1 cm 2/V-sec are reported. These devices were fabricated by techniques compatible with the production of large area liquid crystal displays.

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Improved Performance p-type Polymer (P3HT) / n-type Nanotubes (WS2) Electrolyte Gated Thin-Film Transistor

MRS Advances ◽

10.1557/adv.2018.311 ◽

2018 ◽

Vol 3 (27) ◽

pp. 1525-1533 ◽

Cited By ~ 1

Author(s):

Eleonora Macchia ◽

Alla Zak ◽

Rosaria Anna Picca ◽

Kyriaki Manoli ◽

Cinzia Di Franco ◽

...

Keyword(s):

Thin Film ◽

Threshold Voltage ◽

Field Effect ◽

Thin Film Transistor ◽

Fold Increase ◽

Field Effect Mobility ◽

Figures Of Merit ◽

Electronic Channel ◽

Improved Performance ◽

P Type

ABSTRACTThis work decribes the enhancement of the electrical figures of merit of an Electrolyte Gated Thin-Film Transistor (EG-TFT) comprising a nanocomposite of n-type tungsten disulfide (WS2) nanotubes (NTs) dispersed in a regio-regular p-type poly(3-hexylthiophene-2,5-diyl) (P3HT) polymeric matrix. P3HT/WS2 nanocomposites loaded with different concentrations of NTs, serving as EG-TFTs electronic channel materials have been studied and the formulation has been optimized. The resulting EG-TFTs figures of merit (field-effect mobility, threshold voltage and on-off ratio) are compared with those of the device comprising a bare P3HT semiconducting layer. The optimized P3HT/WS2 nanocomposite, comprising a 60% by weight of NTs, results in an improvement of all the elicited figures of merit with a striking ten-fold increase in the field-effect mobility and the on/off ratio along with a sizable enhancement of the in-water operational stability of the device.

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Vertical Conduction in the New Field Effect Transistors: p-Type and n-Type Vertical Channel Thin Film Transistors

International Journal of High Speed Electronics and Systems ◽

10.1142/s0129156414500232 ◽

2014 ◽

Vol 23 (03n04) ◽

pp. 1450023 ◽

Cited By ~ 1

Author(s):

Olivier Bonnaud ◽

Peng Zhang ◽

Emmanuel Jacques ◽

Regis Rogel

Keyword(s):

Thin Film ◽

Leakage Current ◽

Thin Film Transistors ◽

Field Effect ◽

Field Effect Transistors ◽

Substrate Surface ◽

Vertical Channel ◽

Electrical Behavior ◽

Research Activities ◽

P Type

In order to pursue the integration, the research activities were oriented during the last years towards channel conduction in a plan perpendicular to the substrate surface while in the traditional architectures the conduction is parallel to the surface, under the gate. In the integrated technologies, this approach led to the FinFET. But in this case, even though the conduction plan is perpendicular to the substrate surface, the direction of the drain currents remains parallel to the substrate. New electronics devices were designed with the channels vertically oriented. In the monolithic technologies, many drawbacks have stopped this trend. However, in the case of thin film technologies, the approach appeared more suitable. The channel conduction is thus vertically oriented. But a drawback comes from the leakage current flowing between source and drain. The introduction of an insulating barrier in-between and the decrease of the thickness of the channel active layer, led to electrical behavior much more suitable for applications. After an overview of the different approaches developed as well in monolithic technologies as in thin film technologies, this presentation will give details on the concept and on the fabrication process of quasi-vertical thin film transistors. The associated electrical results will be described, analyzed and commented.

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Performance Comparison of Interdigitated Thin-Film Field-Effect Transistors Using Different Purity Semiconducting Carbon Nanotubes

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.181-182.343 ◽

2011 ◽

Vol 181-182 ◽

pp. 343-348

Author(s):

K.C. Narasimhamurthy ◽

Roy Paily Palathinkal

Keyword(s):

Thin Film ◽

Carbon Nanotube ◽

Hafnium Oxide ◽

Field Effect ◽

Dielectric Material ◽

Field Effect Transistors ◽

Gate Oxide ◽

Channel Length ◽

Performance Comparison ◽

Saturation Region

In this paper, we present the fabrication and characterization of semiconducting carbon nanotube thin-film field-effect transistors (SN-TFTs). High-k dielectric material, hafnium-oxide (HfOX) is used as the gate-oxide of the device. A Thin-film of semi-conducting single walled carbon nanotube (SWCNT) is deposited on the amino-silane modified HfOX surface. Two types of SN-TFTs with interdigitated source and drain contacts are fabricated using 90% and 95% purity of semiconducting SWCNTs (s-SWCNT), have exhibited a p-type behavior with a distinct linear and saturation region of operation. For 20 µm channel length SN-TFT with 95% pure s-SWCNTs has a peak on-off current ratio of 3.5×104 and exhibited a transconductance of 950 µS. The SN-TFT fabricated with HfOX gate oxide has shown a steep sub-threshold slope of 750 mV/decade and threshold voltage of -0.7 V. The SN-TFT of channel length 50 µm has exhibited a maximum mobility of 26.9 cm2/V•s.

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Time-of-Flight Technique Limits of Applicability for Thin-Films of Π-Conjugated Polymers

MRS Proceedings ◽

10.1557/opl.2012.262 ◽

2012 ◽

Vol 1402 ◽

Cited By ~ 2

Author(s):

Marco R. Cavallari ◽

Vinicius R. Zanchin ◽

Cleber A. Amorim ◽

Gerson dos Santos ◽

Fernando J. Fonseca ◽

...

Keyword(s):

Thin Films ◽

Conjugated Polymers ◽

Field Effect ◽

Field Effect Transistors ◽

Time Of Flight ◽

Hole Mobility ◽

Current Mode ◽

Phenylene Vinylene ◽

Polymeric Semiconductor ◽

Order Of Magnitude

ABSTRACTTime of flight (ToF) is the most straightforward technique to determine polymeric semiconductor mobility for electronic applications. We demonstrate ToF limits of applicability to amorphous PPV derivatives, such as poly[2-methoxy-5-(3’,7’-dimethylloctyloxy)-1-4-phenylene vinylene] (MDMO-PPV) and poly[2-methoxy-5-(2’-ethylhexyloxy)-1-4-phenylene vinylene] (MEH-PPV), and polycrystalline poly(3-hexylthiophene) (P3HT). Hole and electron mobility (μ) in submicrometric films (200 – 500 nm) is overestimated compared to casted layers, due to reduced absorption capability, which is confirmed by Charge Extraction by Linearly Increasing Voltage (CELIV) measurements. Charge transport properties in nanometric films, such as for Field-Effect Transistors (FET), can not be studied by current-mode ToF. Hole mobility of ca. 10-5 cm2/Vs with Poole-Frenkel behavior for PPV derivatives and 10-3 cm2/Vs for P3HT is at least one order of magnitude higher than ToF results.

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