scholarly journals Performance Analysis of Tunnel FET Based Ring Oscillator Using Sentaurus TCAD

2021 ◽  
Author(s):  
Menka Yadav
Keyword(s):  
Supply Voltage ◽  
Power Supplies ◽  
Ring Oscillator ◽  
Voltage Controlled Oscillator ◽  
Tunnel Fet ◽  
Simulation Based ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Tcad Simulation ◽  
Device Properties

Abstract A detailed Sentaurus TCAD simulation based study for Silicon Double Gate Tunnel Field Effect Transistor (Si-DG TFET) based Ring Oscillator (RO) is presented in this work. Two different ring oscillator topologies (simple RO and Negative Skewed Delay RO)are presented with two different structures for TFET device. The two structures are different in the source-drain extension regions widths. The extension region width variation effects are studied and presented for inverter and ring oscillator. A TFET based inverter is presented to show the changes in behavior due to variations in the drain extension region widths, which is later used for RO designs. The drain extension region width changes the drain extension region resistances which in turn is responsible for change in the corresponding device properties. RO simulation are used for calculating the delay. To further explore digital and analog applications transfer characteristics and noise margins of inverter are explored with power supplies variations. Better reliability for oscillation frequency is obtained using Negative Skewed Delay ring oscillator (NSD RO) topology. NSD RO is resulting in lesser jitter, more reliable frequency as compared to single-ended ring oscillator topology. By tuning the supply voltage of the device the ring oscillator frequency can be used for RF applications, thus it works like a voltage controlled oscillator (VCO).

scholarly journals Performance analysis of Tunnel FET based Ring Oscillator using Sentaurus TCAD

2021 ◽  
Author(s):  
Menka Yadav
Keyword(s):  
Supply Voltage ◽  
Power Supplies ◽  
Ring Oscillator ◽  
Voltage Controlled Oscillator ◽  
Tunnel Fet ◽  
Simulation Based ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Tcad Simulation ◽  
Device Properties

Abstract A detailed Sentaurus TCAD simulation based study for Silicon Double Gate Tunnel Field Effect Transistor (Si-DG TFET) based Ring Oscillator (RO) is presented in this work. Two different ring oscillator topologies (simple RO and Negative Skewed Delay RO )are presented with two different structures for TFET device. The two structures are different in the source-drain extension regions widths. The extension region width variation effects are studied and presented for inverter and ring oscillator. A TFET based inverter is presented to show the changes in behavior due to variations in the drain extension region widths, which is later used for RO designs. The drain extension region width changes the drain extension region resistances which in turn is responsible for change in the corresponding device properties. RO simulation are used for calculating the delay. To further explore digital and analog applications transfer characteristics and noise margins of inverter are explored with power supplies variations. Better reliability for oscillation frequency is obtained using Negative Skewed Delay ring oscillator (NSD RO) topology. NSD RO is resulting in lesser jitter, more reliable frequency as compared to single-ended ring oscillator topology. By tuning the supply voltage of the device the ring oscillator frequency can be used for RF applications, thus it works like a voltage controlled oscillator (VCO).

scholarly journals Demonstration of Fin-Tunnel Field-Effect Transistor with Elevated Drain

Micromachines ◽  
2019 ◽  
Vol 10 (1) ◽  
pp. 30 ◽  
Author(s):  
Jang Hyun Kim ◽  
Hyun Woo Kim ◽  
Garam Kim ◽  
Sangwan Kim ◽  
Byung-Gook Park
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Electrical Performance ◽  
Control Group ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Tcad Simulation ◽  
High Level ◽  
Aided Design

In this paper, a novel tunnel field-effect transistor (TFET) has been demonstrated. The proposed TFET features a SiGe channel, a fin structure and an elevated drain to improve its electrical performance. As a result, it shows high-level ON-state current (ION) and low-level OFF-state current (IOFF); ambipolar current (IAMB). In detail, its ION is enhanced by 24 times more than that of Si control group and by 6 times more than of SiGe control group. The IAMB can be reduced by up to 900 times compared with the SiGe control group. In addition, technology computer-aided design (TCAD) simulation is performed to optimize electrical performance. Then, the benchmarking of ON/OFF current is also discussed with other research group’s results.

scholarly journals TCAD simulation of a double L‐shaped gate tunnel field‐effect transistor with a covered source–channel

2020 ◽  
Vol 15 (4) ◽  
pp. 272-276 ◽  
Author(s):  
Haiwu Xie ◽  
Hongxia Liu ◽  
Tao Han ◽  
Wei Li ◽  
Shupeng Chen ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Tcad Simulation

scholarly journals Source-All-Around Tunnel Field-Effect Transistor (SAA-TFET): Proposal and Design

2019 ◽  
Author(s):  
Ahmed Shaker ◽  
Ahmed Maged ◽  
Ali Elshorbagy ◽  
Abdallh AbouElainain ◽  
Mona Elsabbagh
Keyword(s):  
Electric Field ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Cutoff Frequency ◽  
Tunneling Junction ◽  
Current Ratio ◽  
Junction Area ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Tcad Simulation

In this paper, a new source-all-around tunnel field-effect transistor (SAA-TFET) is proposed and investigated by using TCAD simulation. The tunneling junction in the SAA-TFET is divided laterally and vertically with respect to the channel direction which provides a relatively large tunneling junction area. An n+ pocket design is also introduced around the source to enhance tunneling rates and improve the device characteristics. In addition, the gate and n+ pocket region also overlap in the vertical and the lateral directions resulting in an enhanced electric field and, in turn, the ON-state current of the SAA-TFET is highly increased compared with the conventional TFET. Promising results in terms of DC (I ON , I OFF , ON/OFF current ratio and SS) and analog (cutoff frequency) performance are obtained for low (V DD = 0.5 V) and high (V DD = 1 V) supply voltages.

scholarly journals Modeling of MoS2 Tunnel Field Effect Transistor in Verilog-A for VLSI Circuit Design

2021 ◽  
Author(s):  
Md Azmot Ullah Khan ◽  
Naheem Olakunle Adesina ◽  
Jian Xu
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Ring Oscillator ◽  
Limiting Factor ◽  
Vlsi Circuit ◽  
Half Adder ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Output Characteristics ◽  
Power Delay Product

Abstract This paper presents the design of an inverter, half adder, and ring oscillator using compact models of MoS2 channel-based tunnel field effect transistor (TFET). The TFET models (both n and p-type) are written in high-level hardware language Verilog-Analog (Verilog-A) following the analytical model of [1] and the output characteristics of the components are simulated in Cadence/Spectre software. The performance of the designed inverter (a basic building block of VLSI circuit) is analyzed by extracting its different parameters, such as transfer characteristics, power dissipation and consumption, delay, power delay product. The simulated outputs (sum & carry) obtained from the half adder circuit exactly match the truth table of the circuit. Moreover, our observation reveals that the ring oscillator can operate at a higher frequency with lower power consumption in comparison to the existing CMOS and GFET technologies. We have also reported an improvement to the limiting factor of ring oscillator performance i.e. phase noise at two different offset frequencies. With all the output characteristics obtained from the commercial software simulation, we expect our model to be applicable to a real-time low-power VLSI circuit.

Dual Metal Triple-gate-dielectric (DM_TGD) Tunnel Field Effect Transistor: A Novel Structure for Future Energy Efficient Device

2021 ◽  
Vol 14 ◽  
Author(s):  
Ajay Kumar Singh ◽  
Tan Chun Fui
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Gate Dielectric ◽  
Supply Voltage ◽  
Effective Dielectric Constant ◽  
Drive Current ◽  
Effect Transistor ◽  
Ambipolar Current ◽  
Tunnel Field Effect Transistor ◽  
Dual Metal

Background: Power reduction is a severe design concern for submicron logic circuits, which can be achieved by scaling the supply voltage. Modern Field Effect Transistor (FET) circuits require at least 60 mV of gate voltage for a better current drive at room temperature. The tunnel Field Effect Transistor (TFET) is a leading future device due to its steep subthreshold swing (SS), making its ideal device at a low power supply. Steep switching TFET can extend the supply voltage scaling with improved energy efficiency for digital and analog applications. These devices suffer from a sizeable ambipolar current, which cannot be reduced using Dual Metal Gate (DMG) alone. Gate dielectric materials play a crucial role in suppressing the ambipolar current. Objective: This paper presents a new structure known as triple-gate-dielectric (DM_TGD) TFET, which combines the dielectric and work function engineering to solve these problems. Method: The proposed structure uses DMG with three dielectric gate materials titanium oxide (TiO2), aluminum oxide (Al2O3), and silicon dioxide (SiO2). The high dielectric material alone as gate oxide increases the fringing fields, which results in higher gate capacitance. This structure has been simulated using 2-D ATLAS simulator in terms of drive current (Ion), ambipolar current (Iamb) and transconductance (gm). Results: The device offers better gm, lower SS, lower leakage and larger drive currents due to weaker insulating barriers at the tunneling junction. Also, higher effective dielectric constant gives better gate coupling and lower trap density. Conclusion: The proposed structure suppresses the ambipolar current and enhance the drive current with reduced SCEs.

scholarly journals Analysis on Tunnel Field-Effect Transistor with Asymmetric Spacer

2020 ◽  
Vol 10 (9) ◽  
pp. 3054
Author(s):  
Hyun Woo Kim ◽  
Daewoong Kwon
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Model Parameters ◽  
Tunnel Fet ◽  
Drain Side ◽  
Fringing Field ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
The Impact

Tunnel field-effect transistor (Tunnel FET) with asymmetric spacer is proposed to obtain high on-current and reduced inverter delay simultaneously. In order to analyze the proposed Tunnel FET, electrical characteristics are evaluated by technology computer-aided design (TCAD) simulations with calibrated tunneling model parameters. The impact of the spacer κ values on tunneling rate is investigated with the symmetric spacer. As the κ values of the spacer increase, the on-current becomes enhanced since tunneling probabilities are increased by the fringing field through the spacer. However, on the drain-side, that fringing field through the drain-side spacer increases ambipolar current and gate-to-drain capacitance, which degrades leakage property and switching response. Therefore, the drain-side low-κ spacer, which makes the low fringing field, is adapted asymmetrically with the source-side high-κ spacer. This asymmetric spacer results in the reduction of gate-to-drain capacitance and switching delay with the improved on-current induced by the source-side high-κ spacer.

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