scholarly journals Improved DC Performance Analysis of a Novel Asymmetric Extended Source Tunnel FET for Fast Switching Application

2021 ◽  
Author(s):  
RITAM DUTTA ◽  
T.D. Subash ◽  
Nitai Paitya
Keyword(s):  
Source Region ◽  
Field Variation ◽  
Extended Source ◽  
Corner Effect ◽  
Fast Switching ◽  
Novel Structure ◽  
Electric Field Variation ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Numerical Device

Abstract A two-dimensional analytical model for asymmetric extended source tunnel field effect transistor (AES-TFET) has been developed to obtain better device performance. The proposed device model has been analytically modelled and performed by solving 2-D Poisson’s equation. Surface potential distribution, electric field variation and band-to-band tunneling (BTBT) rate have been investigated by this numerical modelling. The source region of novel structure of TFET has been extended (varied 2 nm to 6 nm) to incorporate corner effect, which allows BTBT through a thin tunneling barrier, with controlled ambipolar conduction. This eventually produces better source-channel interface tunneling for a n-channel AES-TFET. 2-D numerical device simulator (SILVACO TCAD) has been used for simulation work. The simulated work has been finally validated by analytical modelling of AES-TFET. Better ION, IOFF and switching ratio has been obtained from this novel TFET structure.

scholarly journals Physics Based Analytical Modeling of Asymmetric Elevated Source Tunnel FET (AES-TFET) for Better Tunnel Junction Device (TJD) Performance

2021 ◽  
Author(s):  
RITAM DUTTA ◽  
T.D. Subash ◽  
Nitai Paitya
Keyword(s):  
Tunnel Junction ◽  
Carrier Transport ◽  
Analytical Modelling ◽  
Field Variation ◽  
Corner Effect ◽  
Junction Device ◽  
Electric Field Variation ◽  
Effect Transistor ◽  
Numerical Device ◽  
Elevated Source

Abstract In this paper, a two-dimensional analytical model for asymmetric elevated source tunnel field effect transistor (AES-TFET) has been developed to obtain better tunnel junction device performance. Device physics based analytical modelling is performed by solving 2-D Poisson’s equation. Surface potential distribution, electric field variation and band-to-band tunneling (B2B) rate have been investigated by this numerical modelling. In our proposed structure, the source has been elevated (varied 2 nm to 6 nm) to incorporate corner effect; which boosts the carrier transport via thin tunneling barrier, with controlled ambipolar conduction. This eventually produces better source-channel interface tunneling for a n-channel AES-TFET structure. 2-D numerical device simulator (SILVACO TCAD) has been used for simulation work. The simulated graphical representations have been finally validated by analytical modelling of AES-TFET.

scholarly journals Study And Investigation of Silicon Extended Source Vertical Double Gate Tunnel Transistor For Analog/RF Performance

2021 ◽  
Author(s):  
omendra Kumar singh ◽  
D Vaithiyanathan ◽  
Baljit Kaur
Keyword(s):  
Structural Parameters ◽  
Source Region ◽  
Cutoff Frequency ◽  
Double Gate ◽  
Carrier Injection ◽  
Extended Source ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Rf Performance ◽  
Silvaco Atlas

Abstract In this paper, a Silicon Double Gate tunnel field effect transistor with Extended Source (ESVDG-TFET) is disclosed while addressing the need for dc/switching and analog/RF applications using Silvaco-Atlas simulator which is used to examine and explore the performance of the proposed device. The mechanics of band-to-band tunnelling and accompanying carrier injection are used to illustrate the operation of the proposed silicon ESVDG-TFET device. The gate is designed to overlap with extended source region along with N+ pockets and channel in order to facilitate both the lateral and vertical tunnelling . The silicon ESVDG-TFET provide lower subthreshold swing of 10.1 mV/decade that allow higher ratio of ION / IOFF of 1013 for optimized device structural parameters with threshold voltage of 0.35 V. Moreover, peak transconductance of 800 uS/ um, cutoff frequency of 82 GHz, gain bandwidth product of 16.8 GHz and transit time of 1p sec is obtained by proposed device.

Temperature Sensitivity Analysis of Extended Source Double Gate Tunnel Field Effect Transistor

2021 ◽  
Author(s):  
Dharmender Nishad ◽  
Kaushal Nigam ◽  
Satyendra Kumar
Keyword(s):  
Temperature Sensitivity ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Effect Of Temperature ◽  
Double Gate ◽  
Extended Source ◽  
Temperature Variations ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

Abstract Temperature-induced performance variation is one of the main concerns of the conventional stack gate oxide double gate tunnel field-effect transistor (SGO-DG-TFET). In this regard, we investigate the temperature sensitivity of extended source double gate tunnel field-effect transistor (ESDG-TFET). For this, we have analyzed the effect of temperature variations on the transfer characteristics, analog/RF, linearity and distortion figure of merits (FOMs) using technology computer aided design (TCAD) simulations. Further, the temperature sensitivity performance is compared with conventional SGO-DG-TFET. The comparative analysis shows that ESDG-TFET is less sensitive to temperature variations compared to the conventional SGO-DG-TFET. Therefore, this indicates that ESDG-TFET is more reliable for low-power, high-frequency applications at a higher temperature compared to conventional SGO-DG-TFET.

Structural Modification of Doped Tunnel Field Effect Transistor for Enhanced Conduction Current and Lower Subthreshold Swing

2019 ◽  
Vol 14 (11) ◽  
pp. 1539-1547
Author(s):  
Deepak Soni ◽  
Amit Kumar Behera ◽  
Dheeraj Sharma ◽  
Dip Prakash Samajdar ◽  
Dharmendra Singh Yadav
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Metal Layer ◽  
Source Region ◽  
Subthreshold Swing ◽  
Electrical Characteristics ◽  
Gate Electrode ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Rf Performance

The material solubility in the source region and abrupt source/channel junction profile are the major concern which is responsible for the improvement of the electrical characteristics of conventional physical doped tunnel field effect transistor (PD-TFET). For this, an additional negatively polarised electrode is mounted in P+ (source) – N (channel) – N+ (drain) structure over the source region to overcome material solubility. This improves the electrical characteristics of the device. Along with this, we have implanted a low workfunction metal layer (ML) in the oxide layer under the gate electrode for creating more abruptness at the junction to improve the subthreshold swing (SS) of the device. Thus, the proposed concept improves the DC/RF performance of the doped TFET device. Further to this, the optimization of metal layer workfunction and misalignment of metal layer in TFET have been performed to get optimum device characteristics. In addition to this, for the suppression of ambipolar behaviour, gate electrode is shorted from the drain side. Due to short length of gate electrode tunneling barrier width at the drain/channel junction increases, hence the tunneling probability decreases which reduces the ambipolar current to parasitic current. Shortening of gate electrode also improves the RF performance.

scholarly journals Optimization of Tunnel Field-Effect Transistor-Based ESD Protection Network

Crystals ◽  
2021 ◽  
Vol 11 (2) ◽  
pp. 128
Author(s):  
Zhihua Zhu ◽  
Zhaonian Yang ◽  
Xiaomei Fan ◽  
Yingtao Zhang ◽  
Juin Jei Liou ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Source Region ◽  
Potential Candidate ◽  
Protection Scheme ◽  
Esd Protection ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Aided Design

The tunnel field-effect transistor (TFET) is a potential candidate for replacing the reverse diode and providing a secondary path in a whole-chip electrostatic discharge (ESD) protection network. In this paper, the ESD characteristics of a traditional point TFET, a line TFET and a Ge-source TFET are investigated using technology computer-aided design (TCAD) simulations, and an improved TFET-based whole-chip ESD protection scheme is proposed. It is found that the Ge-source TFET has a lower trigger voltage and higher failure current compared to the traditional point and line TFETs. However, the Ge-source TFET-based secondary path in the whole-chip ESD protection network is more vulnerable compared to the primary path due to the low thermal instability. Simulation results show that choosing the proper germanium mole fraction in the source region can balance the discharge ability and thermal failure risk, consequently enhancing the whole-chip ESD robustness.

scholarly journals Impactful Study of F-shaped Tunnel FET

2021 ◽  
Author(s):  
PRABHAT SINGH ◽  
DHARMENDRA SINGH YADAV
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Source Region ◽  
Gate Oxide ◽  
Crowding Effect ◽  
Turn On ◽  
Tunnel Fet ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
The Impact

Abstract In this proposed work, a novel single gate F-shaped channel tunnel field effect transistor (SG-FC-TFET) is proposed and investigated. The impact of thickness of the source region and lateral tunneling length between the gate oxide and edge of the source region on analog and radio frequency parameters are investigated with appropriate source and drain lateral length through the 2D-TCAD tool. The slender shape of the source enhanced the electric le crowding effect at the corners of the source region which reflect in term of high On-current (Ion). The Ion of proposed device is increased up to 10-4 A=μm with reduced sub-threshold swing (SS) is 7.3 mV/decade and minimum turn-ON voltage (Von = 0.28 V). The analog/RF parameters of SG-FC-TFET are optimized.

scholarly journals Study of a Gate-Engineered Vertical TFET with GaSb/GaAs0.5Sb0.5 Heterojunction

Materials ◽  
2021 ◽  
Vol 14 (6) ◽  
pp. 1426
Author(s):  
Haiwu Xie ◽  
Yanning Chen ◽  
Hongxia Liu ◽  
Dan Guo
Keyword(s):  
Field Effect Transistor ◽  
Performance Enhancement ◽  
Source Region ◽  
Gain Bandwidth ◽  
Source Voltage ◽  
Effect Transistor ◽  
Work Functions ◽  
Tunnel Field Effect Transistor ◽  
And Control ◽  
Dual Material

It is well known that the vertical tunnel field effect transistor (TFET) is easier to fabricate than the conventional lateral TFETs in technology. Meanwhile, a lightly doped pocket under the source region can improve the subthreshold performance of the vertical TFETs. This paper demonstrates a dual material gate heterogeneous dielectric vertical TFET (DMG-HD-VTFET) with a lightly doped source-pocket. The proposed structure adopts a GaSb/GaAs0.5Sb0.5 heterojunction at the source and pocket to improve the band-to-band tunneling (BTBT) rate; at the same time, the gate electrode is divided into two parts, namely a tunnel gate (M1) and control gate (M2) with work functions ΦM1 and ΦM2, where ΦM1 > ΦM2. In addition, further performance enhancement in the proposed device is realized by a heterogeneous dielectric corresponding to a dual material gate. Simulation results indicate that DMG-HD-VTFET and HD-VTFET possess superior metrics in terms of DC (Direct Current) and RF (Radio Frequency) performance as compared with conventional VTFET. As a result, the ON-state current of 2.92 × 10−4 A/μm, transconductance of 6.46 × 10−4 S/μm, and average subthreshold swing (SSave) of 18.1 mV/Dec at low drain voltage can be obtained. At the same time, DMG-HD-VTFET could achieve a maximum fT of 459 GHz at 0.72 V gate-to-source voltage (Vgs) and a maximum gain bandwidth (GBW) of 35 GHz at Vgs = 0.6 V, respectively. So, the proposed structure will have a great potential to boost the device performance of traditional vertical TFETs.

Drain Current Modeling of Tunnel FET using Simpson’s Rule

2021 ◽  
Author(s):  
Arun A V ◽  
Minu K K ◽  
Sreelakshmi P S ◽  
Jobymol Jacob
Keyword(s):  
Energy Efficient ◽  
Field Effect Transistor ◽  
Drain Current ◽  
Generation Rate ◽  
Tunnel Fet ◽  
Simpson’S Rule ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Numerical Device ◽  
Simpson's Rule

Abstract Tunnel Field Effect Transistor can be introduced as an emerging alternate to MOSFET which is energy efficient and can be used in low power applications. Due to the challenge involved in integration of band to band tunneling generation rate, the existing drain current models are inaccurate. A compact analytical model for simple tunnel FET and pnpn tunnel FET is proposed which is highly accurate. The numerical integration of tunneling generation rate in the tunneling region is performed using Simpson’s rule. Integration is done using both Simpson’s 1/3 rule and 3/8 rule and the models are validated against numerical device simulations. The models are compared with existing models and it is observed that the proposed models show excellent agreement with device simulations in the entire region of operation with Simpson’s 3/8 rule exhibiting the maximum accuracy.

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