Polarization isolation for GaN electronics

GaN electronics have hinged on invasive isolation such as mesa etching and ion implantation to define device geometry and reduce off-state leakage, which however suffer from damages hence potential leakage paths and complex processing. In this study, we propose a new paradigm of polarization isolation utilizing intrinsic electronic properties, realizing in-situ isolation during device epitaxy without the need of post-growth processing. Specifically, adjacent III- and N-polar AlGaN/GaN heterojunctions were grown simultaneously on the patterned AlN nucleation layer on c-plane sapphire substrates. The two-dimensional electron gas (2DEG) was formed at the III-polar regions but completely depleted in the N-polar regions, thereby isolating the 2DEG channels with a large 3.5 eV barrier as predicted by theoretical simulations. The polarization-isolated high electron mobility transistors (PI-HEMT) structures exhibited significantly reduced isolation leakage currents by up to nearly two orders of magnitude at 50 V voltage bias compared to the state-of-the-art results with various isolation spacing. Besides, record-high isolation breakdown voltage of 2628 V was demonstrated for the PI-HEMT structure with 3 µm isolation spacing. Moreover, the PI-HEMT device show low off-state leakage current of 2×10− 8 mA/mm with high Ion/Ioff ratio of 109 at VD=2 V and nearly ideal subthreshold slope of 61 mV/dec. This work demonstrates that the polarization isolation is highly promising for GaN electronics, in particular for high-density integration requiring precisely-defined patterns amid small device spacing.