Low-Temperature Annealing of CdZnTeSe under Bias

We performed a gradual low-temperature annealing up to 360 K on a CdZnTeSe radiation detector equipped with gold and indium electrodes under bias at both polarities. We observed significant changes in the detector’s resistance and space-charge accumulation. This could potentially lead to the control and improvement of the electronic properties of the detector because the changes are accompanied with the reduction in the bulk dark current and surface leakage current. In this article, we present the results of a detailed study of the internal electric field and conductivity changes in CdZnTeSe detector for various annealing steps under bias taking into account different polarities during annealing and subsequent characterization. We observed that low-temperature annealing results in an increase in the barrier height at the contacts that, in general, reduces the dark current and decreases the positive space charge present in the sample compared to the pre-annealed condition.

Electrical characteristics of silicon differential photoreceivers

The volt-ampere curve of silicon differential photodiodes were measured. It was found that the current-voltage curve of the photodiodes of the main and additional channels had a similar shape, without revealing a significant dependence on the implantation dose of the additional channel. The main parameters of the equivalent circuits of photodiodes are determined. In the reverse branch, the dominant impact was exerted by the surface leakage conductivity with a differential resistance of about 10 GΩ. Measurements from minus 60 °C to 60 °C showed that when using amplifiers with an input impedance of about 103 Ω, differential photoreceivers can be successfully used as selective short-wavelength and two-color ones.

Analysis of the LNAPL Migration Process in the Vadose Zone under Two Different Media Conditions

This study focused on the processes of free infiltration, precipitation displacement, and natural attenuation of the LNAPL under the condition of near-surface leakage. Sandbox experiments were performed to explore the migration characteristics of LNAPL in the vadose zone with two media structures and the influences of the soil interface on the migration of LNAPL. The results indicate that the vertical migration velocity of the LNAPL infiltration front in medium and coarse sand was 1 order of magnitude higher than that in fine sand and that the LNAPL accumulated at the coarse–fine interface, which acted as the capillary barrier. Displacement of precipitation for LNAPL had little relationship with rainfall intensity and was obviously affected by medium particle size, where coarse sand (40.78%) > medium sand (20.5%) > fine sand (10%). The natural attenuation rate of the LNAPL in the vadose zone was related to the water content of the media; the natural attenuation rate of fine sand was higher. This study simulated the process of the LNAPL leakage from the near surface into the layered heterogeneous stratum, improved the understanding of the migration of the LNAPL under different stratum conditions, and can provide support for the treatment of LNAPL leakage events in the actual site.

Understanding Variations in the Tracking and Erosion Performance of HTV-SR-Based Composites due to AC-Stressed Aging

Among the polymeric family, high-temperature-vulcanized silicone rubber (HTV-SR) is the most deployed material for high voltage insulation applications. However, in an outdoor environment, due to contamination and wetting-induced dry band arcing, consequently SR experiences surface tracking and erosion. From a practical standpoint, the tracking and erosion performance under multi-stress aging is required to be known. It is in that context that the present study was undertaken to measure and analyze the effect of multi-stress aging on tracking and erosion performance. Composite samples of SR having different filler concentrations of silica and alumina trihydroxide (ATH) were aged in a multi-stress chamber for a period of 5000 h, and after that their electrical tracking performance was studied. Simultaneously, unaged samples were also exposed to tracking test for comparison. To conduct this test, the inclined plane testing technique was used in accordance with IEC-60587. All samples exposed to tracking test were analyzed using different diagnostic and measuring techniques involving surface leakage current measurement, Fourier transform infrared spectroscopy (FTIR), thermal stability and hydrophobicity classification. Experimental results shown that the tracking lifetime increased through incorporation of silica and ATH fillers in the SR. Amongst all test samples, two samples designated as filled with 2% nano silica and 20% micro silica/ATH exhibited greater resistance to tracking. This was attributed to the optimum loading as well as better dispersion of the fillers in the polymer matrix. The presence of nano-silica enhanced time-to-tracking failure, owing to both improved thermal stability and enhanced shielding effect on the surface of nanocomposite insulators.

High Performance p-i-n Photodetectors on Ge-on-Insulator Platform

In this article, we demonstrated novel methods to improve the performance of p-i-n photodetectors (PDs) on a germanium-on-insulator (GOI). For GOI photodetectors with a mesa diameter of 10 μm, the dark current at −1 V is 2.5 nA, which is 2.6-fold lower than that of the Ge PD processed on Si substrates. This improvement in dark current is due to the careful removal of the defected Ge layer, which is formed with the initial growth of Ge on Si. The bulk leakage current density and surface leakage density of the GOI detector at −1 V are as low as 1.79 mA/cm2 and 0.34 μA/cm, respectively. GOI photodetectors with responsivity of 0.5 and 0.9 A/W at 1550 and 1310 nm wavelength are demonstrated. The optical performance of the GOI photodetector could be remarkably improved by integrating a tetraethylorthosilicate (TEOS) layer on the oxide side due to the better optical confinement and resonant cavity effect. These PDs with high performances and full compatibility with Si CMOS processes are attractive for applications in both telecommunications and monolithic optoelectronics integration on the same chip.