scholarly journals Assessment of Interface Trap Charges on Proposed TFET for Low Power High-frequency Application

2021 ◽  
Author(s):  
Sachin Kumar ◽  
Dharmendra Singh Yadav
Keyword(s):  
Low Power ◽  
High Frequency ◽  
Superior Performance ◽  
Interface Trap ◽  
Performance Parameters ◽  
Metal Gate ◽  
Ultra Low Power ◽  
Dual Metal ◽  
The Impact ◽  
Trap Charges

Abstract Accumulation of trap charges at the semiconductor and oxide interface is the most dominating factor and cannot be neglected as it degrades device performance and reliability. This manuscript, presents detailed investigation to analyze the impact of interface trap charges (ITCs) on the performance parameters of the proposed device i.e., heterogeneous dielectric dual metal gate step channel TFET (HD DMG SC-TFET). The comparative study is conducted with dual metal gate step channel TEFT (DMG SC-TFET). The proposed device shows improved current carrying capability, suppressed ambipolar behaviour with steeper subthreshold swing. The purpose of this study to determine the ITCs impact on DC characteristics and analog/RF electrical performance parameters of the proposed device. It further observed that the proposed device exhibit superior performance due to dielectric engineering at oxide layer. Moreover, advanced communication devices must respond linearly therefore, the impact of ITCs on linearity parameters is also studied. From this brief comparative investigation, it is observed that the proposed TFET exhibits negligible distortion in linearity parameters with little or no impact of trap charges as compared to DMG SC-TFET. Thus, proposed TFET is appropriate for ultra-low power high-frequency electronic devices.

Impact of interface trap charges on Junctionless double and triple metal gate High-k Gate All Around Nanowire FET based Alzheimer Biosensor

2021 ◽  
Author(s):  
Rishu Chaujar ◽  
Mekonnen Getnet Yirak
Keyword(s):  
Threshold Voltage ◽  
Positive Impact ◽  
Drain Current ◽  
Interface Trap ◽  
Metal Gate ◽  
High K ◽  
Current Threshold ◽  
Subthreshold Voltage ◽  
Output Characteristics ◽  
The Impact

Abstract In this work, junctionless double and triple metal gate high-k gate all around nanowire field-effect transistor-based APTES biosensor has been developed to study the impact of ITCs on device sensitivity. The analytical results were authenticated using ‘‘ATLAS-3D’’ device simulation tool. Effect of different interface trap charge on the output characteristics of double and triple metal gate high-k gate all around junctionless NWFET biosensor was studied. Output characteristics, like transconductance, output conductance,drain current, threshold voltage, subthreshold voltage and switching ratio, including APTES biomolecule, have been studied in both devices. 184% improvement has been investigated in shifting threshold voltage in a triple metal gate compared to a double metal gate when APTES biomolecule immobilizes on the nanogap cavity region under negative ITCs. Based on this finding, drain off-current ratio and shifting threshold voltage were considered as sensing metrics when APTES biomolecule immobilizes in the nanogap cavity under negative ITCs which is significant for Alzheimer's disease detection. We signifies a negative ITC has a positive impact on our proposed biosensor device compared to positive and neutral ITCs.

Hetero‐material CPTFET with high‐frequency and linearity analysis for ultra‐low power applications

2018 ◽  
Vol 13 (11) ◽  
pp. 1609-1614 ◽  
Author(s):  
Dharmendra Singh Yadav ◽  
Dheeraj Sharma ◽  
Sukeshni Tirkey ◽  
Deepak Ganesh Sharma ◽  
Shriya Bajpai ◽  
...  
Keyword(s):  
Low Power ◽  
High Frequency ◽  
Ultra Low Power

scholarly journals The Impact of a Paraelectric layer in the FE/DE Stack on Performance of NCFET

2022 ◽  
Author(s):  
Harshit Kansal ◽  
Aditya S Medury
Keyword(s):  
Low Power ◽  
Layer Thickness ◽  
Remnant Polarization ◽  
Design Space ◽  
Performance Parameters ◽  
Analog Performance ◽  
Wide Range ◽  
The Impact ◽  
Tcad Simulations ◽  
Mfis Structure

<div>In this letter, through TCAD simulations, we show that the introduction of a thin paraelectric (PE) layer between the ferroelectric (FE) and dielectric (DE) layers in an MFIS structure, expands the design space for the FE layer enabling hysteresis-free and steep subthreshold behavior, even with a thicker FE layer. This can be explained by analyzing the FE-PE stack from a capacitance perspective where the thickness of the PE layer in the FE-PE stack has the effect of reducing the FE layer thickness, while also reducing the remnant polarization. Finally, for the same FE-PE-DE stack, analog performance parameters such as $\frac{g_{m}} g_{ds}}$ and $\frac{g_{m}}{I_{d}}$ are analyzed, showing good characteristics over a wide range of gate lengths, at low drain voltages, thus demonstrating applicability for low power applications.</div>

Optimization of Si-doped HfO2 ferroelectric material-based negative capacitance junctionless TFET: Impact of temperature on RF/linearity performance

2020 ◽  
Vol 34 (27) ◽  
pp. 2050242
Author(s):  
Shradhya Singh ◽  
Sangeeta Singh ◽  
Alok Naugarhiya
Keyword(s):  
Temperature Variation ◽  
Ferroelectric Material ◽  
Asymmetric Structure ◽  
Negative Capacitance ◽  
Performance Parameters ◽  
Device Structure ◽  
Ultra Low Power ◽  
Si Doped ◽  
Rf Performance ◽  
The Impact

This paper addresses the effect of temperature variation on the performance of a novel device structure Si-doped Hf[Formula: see text] negative capacitance junctionless tunnel field effect transistor (Si:Hf[Formula: see text] NC-JLTFET). Here, Si:Hf[Formula: see text] ferroelectric material is deployed as gate stack along with high-K gate dielectric Hf[Formula: see text]. Si:Hf[Formula: see text] ferroelectric material generates NC effect during the device operation. This phenomenon is an effective technique for intrinsic voltage amplification, reduction in power supply, as well as minimization of power dissipation. The proposed device structure has two variants, symmetric and asymmetric with respect to the oxide thickness between electrode and Si body at both drain and source sides. As band-to-band tunneling in TFET is temperature dependent, it is very crucial to analyze the impact of temperature variation on the device performance. This work is mainly focused on investigating the device dc performance parameters, analog/RF performance parameters and linearity performance parameters by observing the impact of temperature variation. The device characteristics reveal that for dc and RF performance parameters, asymmetric structure shows better result. Highest [Formula: see text] ratio and minimum SS are reported as [Formula: see text] and 20.038 mV/dec, respectively, at 300K for asymmetric structure. At elevated temperatures higher cutoff frequency and reduced intrinsic delay project the device as a strong candidate for ultra low-power and high switching speed applications. Further, the reported device shows better linearity performance at higher temperatures.

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