An Ultra-low Power, High SNM, High Speed and High Temperature of 6T-SRAM Cell in 3C-SiC 130 nm CMOS Technology

We present three ultra-low-power CMOS circuits: a temperature sensor, a voltage reference and a comparator developed for an ultra-low-power microsystem (ULP-MST) aiming at temperature sensing in harsh environments. The microsystem has 3 main functions: detecting a user-defined temperature threshold T0, generating a wake-up signal that turns on a data-acquisition microprocessor (located in a safe area) above T0, and measuring temperatures above T0. To achieve ultra-low-power operation, the three CMOS circuits are implemented in Silicon-on-Insulator (SOI) CMOS technology and are optimized to work in the subthreshold regime of the transistors. Since our application is mainly for harsh environment (i.e. high temperature and radiation), the chip has been designed using a suitable 1-μm SOI-CMOS technology. Simulations have been performed over the different process corners to verify functionality after fabrication. The typical power dissipation at high temperature (up to 240°C) is less than 100 μW at 5 V supply voltage. Measurements have validated correct operation in the temperature range from −40°C to 300°C before radiation and to 125°C after radiation up to now which will be extended further with a new set-up. Irradiation has been performed from 10 to 30 kGy. Such very high doses cause a shift down of output voltage values, which leads to a change of the temperature detection level and also increases the power dissipation by up to six times. Annealing effects help the partial recovery of the device operation at high temperature and the remote microprocessor enables calibration after radiation to readjust the temperature detection level.

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Ultra-low power and high speed design and implementation of AES and SHA1 hardware cores in 65 nanometer CMOS technology

2009 IEEE International Conference on Electro/Information Technology ◽

10.1109/eit.2009.5189651 ◽

2009 ◽

Cited By ~ 3

Author(s):

Feng Ge ◽

Pranjal Jain ◽

Ken Choi

Keyword(s):

Low Power ◽

High Speed ◽

Cmos Technology ◽

Ultra Low Power ◽

Nanometer Cmos ◽

Design And Implementation ◽

High Speed Design

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Low voltage high speed 8T SRAM cell for ultra-low power applications

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i3.29.18464 ◽

2018 ◽

Vol 7 (3.29) ◽

pp. 70

Author(s):

A S. S. Trinadh Kumar ◽

B V. V. Satyanarayana

Keyword(s):

Low Power ◽

High Speed ◽

Low Voltage ◽

Total Power ◽

Portable Devices ◽

Threshold Region ◽

Ultra Low Power ◽

Read Operation ◽

Sram Cell ◽

Total Power Consumption

The usage of portable devices increasing rapidly in the modern life has led us to focus our attention to increase the performance of the SRAM circuits, especially for low power applications. Basically in six-Transistor (6T) SRAM cell either read or write operation can be performed at a time whereas, in 7T SRAM cell using single ended write operation and single ended read operation both write and read operations will be accomplished simultaneously at a time respectively. When it comes to operate in sub threshold region, single ended read operation will be degraded severely and single ended write operation will be severely degraded in terms of write-ability at lower voltages. To encounter these complications, an eight transistor SRAM cell is proposed. It performs single ended read operation and single ended write operation together even at sub threshold region down to 0.1V with improved read-ability using read assist and improved dynamic write-ability which helps in reducing the consumption of power by attaining a lower data retention voltage point. To reduce the total power consumption in the circuits, two extra access transistors are used in 8T SRAM cell which also helps in reducing the overall delay.

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FAST LOW POWER FREQUENCY SYNTHESIS APPLICATIONS BY USING A DCVSL DELAY CELL

International Journal of Electronics and Electical Engineering ◽

10.47893/ijeee.2015.1159 ◽

2015 ◽

pp. 220-225

Author(s):

N. KUMAR BABU ◽

P. SASIBALA

Keyword(s):

Low Power ◽

High Speed ◽

Schmitt Trigger ◽

Cmos Technology ◽

Propagation Delay ◽

Model Parameters ◽

Cmos Process ◽

Ultra Low Power ◽

Delay Cell ◽

Parasitic Effects

In this paper, we proposed two new structures for differential cascode voltage switch logic (DCVSL) pull-up stage. In conventional DCVSL structure these lies a drawback i.e. low-to-high propagation delay is larger than high-to-low propagation delay which could be reduced by using DCVSL-R. Using resistors in DCVSL-R structure, parasitic effects are coming into picture and it occupies more area on the chip [1]. To minimize these problems we propose a new Ultra Low Power Diode (ULPD) structures in place of resistors. This provides the minimum parasitic effects and occupies less area on the chip. Second one uses Complementary Pass Transistor Logic (CPTL) structure, which provides complementary outputs. This is an alternate circuit for conventional DCVSL structure. The performances of the proposed circuits are examined using cadence and model parameters of a 180nm CMOS process. This simulation result of the two circuits is presented and is compared. These circuits are suitable for VLSI implementation. Secondly, we proposed two new CMOS Schmitt trigger circuits. These Schmitt trigger circuits are evaluated both analytically and numerically with the sources from proposed ULPD ring oscillators. The hysteresis curves of the circuits are presented. The Schmitt triggers introduced here are most suitable for high speed applications. The proposed circuits havebeen designed in TSMC-0.18μm 1.8v CMOS technology and analyzed using spectre from cadence Design systems at 50MHz and 103MHz.

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