scholarly journals Low voltage high speed 8T SRAM cell for ultra-low power applications

2018 ◽  
Vol 7 (3.29) ◽  
pp. 70
Author(s):  
A S. S. Trinadh Kumar ◽  
B V. V. Satyanarayana
Keyword(s):  
Low Power ◽  
High Speed ◽  
Low Voltage ◽  
Total Power ◽  
Portable Devices ◽  
Threshold Region ◽  
Ultra Low Power ◽  
Read Operation ◽  
Sram Cell ◽  
Total Power Consumption

The usage of portable devices increasing rapidly in the modern life has led us to focus our attention to increase the performance of the SRAM circuits, especially for low power applications. Basically in six-Transistor (6T) SRAM cell either read or write operation can be performed at a time whereas, in 7T SRAM cell using single ended write operation and single ended read operation both write and read operations will be accomplished simultaneously at a time respectively. When it comes to operate in sub threshold region, single ended read operation will be degraded severely and single ended write operation will be severely degraded in terms of write-ability at lower voltages. To encounter these complications, an eight transistor SRAM cell is proposed. It performs single ended read operation and single ended write operation together even at sub threshold region down to 0.1V with improved read-ability using read assist and improved dynamic write-ability which helps in reducing the consumption of power by attaining a lower data retention voltage point. To reduce the total power consumption in the circuits, two extra access transistors are used in 8T SRAM cell which also helps in reducing the overall delay.  

scholarly journals Design of Area Efficient, Low-Power and Reliable Transmission Gate-based 10T SRAM Cell for Biomedical Application

2021 ◽  
Author(s):  
Aswini Valluri ◽  
◽  
Sarada Musala ◽  
Muralidharan Jayabalan ◽  
◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Biomedical Application ◽  
Cmos Technology ◽  
Total Power ◽  
Silicon Area ◽  
Transmission Gate ◽  
Read Operation ◽  
Sram Cell ◽  
Total Power Consumption

There is an immense necessity of several kilo bytes of embedded memory for Biomedical systems which typically operate in the sub-threshold domain with perfect efficiency. SRAMs (Static Random Access Memory) dominates the total power consumption and the overall silicon area, as 70% of the die has been occupied by them. This brief proposes the design of a Transmission gate-based SRAM cell for Bio medical application eliminating the use of peripheral circuitry during the read operation. It commences the read operation directly with the help of Transmission gates with which the data stored in the storage nodes can be read, instead of using the precharge and sense amplifier circuits which suits better for the implantable devices. This topology offers smaller area, reduced delay, low power consumption as well as improved data stabilization in the read operation. The cell is implemented in 45nm CMOS technology operated at 0.45V.

Design and Layout of a High-Performance PWM Control Class D Amplifiers IC Systems

2012 ◽  
Vol 203 ◽  
pp. 469-473
Author(s):  
Ruei Chang Chen ◽  
Shih Fong Lee
Keyword(s):  
Low Power ◽  
High Performance ◽  
Low Voltage ◽  
Design Flow ◽  
Total Power ◽  
Cmos Process ◽  
Low Power Circuits ◽  
Class D ◽  
Total Power Consumption ◽  
Power Circuits

This paper presents the design and implementation of a novel pulse width modulation control class D amplifiers chip. With high-performance, low-voltage, low-power and small area, these circuits are employed in portable electronic systems, such as the low-power circuits, wireless communication and high-frequency circuit systems. This class D chip followed the chip implementation center advanced design flow, and then was fabricated using Taiwan Semiconductor Manufacture Company 0.35-μm 2P4M mixed-signal CMOS process. The chip supply voltage is 3.3 V which can operate at a maximum frequency of 100 MHz. The total power consumption is 2.8307 mW, and the chip area size is 1.1497×1.1497 mm2. Finally, the class D chip was tested and the experimental results are discussed. From the excellent performance of the chip verified that it can be applied to audio amplifiers, low-power circuits, etc.

scholarly journals Novel Low Voltage and Low Power Array Multiplier Design for IoT Applications

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1429 ◽  
Author(s):  
Jin-Fa Lin ◽  
Cheng-Yu Chan ◽  
Shao-Wei Yu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Voltage ◽  
Full Adder ◽  
Total Power ◽  
Iot Applications ◽  
Delay Cell ◽  
Total Power Consumption ◽  
Array Multiplier ◽  
Cell Circuit

In this paper, a novel latch-adder based multiplier design, targeting low voltage and low power IoT applications is presented. It employs a semi-dynamic (dynamic circuit with static keeper circuit) full adder design which efficiently incorporates the level sensitive latch circuit with the adder cell. Latch circuit control signals are generated by a chain of delay cell circuits. They are applied to each row of the adder array. This row-wise alignment ensures an orderly procedure, while successfully removing spurious switching resulting in reduced power consumption. Due to the delay cell circuit of our design is also realized by using full adder. Therefore, it is unnecessary to adjust the transistor sizes of the delay cell circuit deliberately. Post-layout simulation results on 8 × 8 multiplier design show that the proposed design has the lowest power consumption of all design candidates. The total power consumption saving compared to conventional array multiplier designs is up to 38.6%. The test chip measurement shows successful operations of our design down to 0.41 V with a power consumption of only 427 nW with a maximum frequency 500 KHz.

scholarly journals Design of an Edge-Detection CMOS Image Sensor with Built-in Mask Circuits

Sensors ◽  
2020 ◽  
Vol 20 (13) ◽  
pp. 3649
Author(s):  
Minhyun Jin ◽  
Hyeonseob Noh ◽  
Minkyu Song ◽  
Soo Youn Kim
Keyword(s):  
Power Consumption ◽  
Edge Detection ◽  
Low Power ◽  
High Speed ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Frame Rate ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Total Power Consumption

In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) that has built-in mask circuits to selectively capture either edge-detection images or normal 8-bit images for low-power computer vision applications. To detect the edges of images in the CIS, neighboring column data are compared in in-column memories after column-parallel analog-to-digital conversion with the proposed mask. The proposed built-in mask circuits are implemented in the CIS without a complex image signal processer to obtain edge images with high speed and low power consumption. According to the measurement results, edge images were successfully obtained with a maximum frame rate of 60 fps. A prototype sensor with 1920 × 1440 resolution was fabricated with a 90-nm 1-poly 5-metal CIS process. The area of the 4-shared 4T-active pixel sensor was 1.4 × 1.4 µm2, and the chip size was 5.15 × 5.15 mm2. The total power consumption was 9.4 mW at 60 fps with supply voltages of 3.3 V (analog), 2.8 V (pixel), and 1.2 V (digital).

A 16.4 nW, Sub-1 V, Resistor-Less Voltage Reference with BJT Voltage Divider

2018 ◽  
Vol 27 (13) ◽  
pp. 1850206 ◽  
Author(s):  
Qingshan Yang ◽  
Peiqing Han ◽  
Niansong Mei ◽  
Zhaofeng Zhang
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Voltage Divider ◽  
Total Power ◽  
Cmos Process ◽  
Operating Voltage ◽  
Voltage Reference ◽  
Ultra Low Power ◽  
Silicon Area ◽  
Total Power Consumption

A 16.4[Formula: see text]nW, sub-1[Formula: see text]V voltage reference for ultra-low power low voltage applications is proposed. This design reduces the operating voltage to 0.8[Formula: see text]V by a BJT voltage divider and decreases the silicon area considerably by eliminating resistors. The PTAT and CTAT are based on SCM structures and a scaled-down [Formula: see text], respectively, to improve the process insensitivity. This work is fabricated in 0.18[Formula: see text][Formula: see text]m CMOS process with a total area of 0.0033[Formula: see text]mm2. Measured results show that it works properly for supply voltage from 0.8[Formula: see text]V to 2[Formula: see text]V. The reference voltage is 467.2[Formula: see text]mV with standard deviation ([Formula: see text]) being 12.2 mV and measured TC at best is 38.7[Formula: see text]ppm/[Formula: see text]C ranging from [Formula: see text]C to 60[Formula: see text]C. The total power consumption is 16.4[Formula: see text]nW under the minimum supply voltage at 27[Formula: see text]C.

scholarly journals Subthreshold Region based Linear Feedback Shift Register

2019 ◽  
Vol 8 (6S2) ◽  
pp. 817-821
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
System Level ◽  
Linear Feedback ◽  
Portable Devices ◽  
Subthreshold Region ◽  
Flip Flop ◽  
Ultra Low Power

Growing demand for portable devices and fast increases in complexity of chip cause power dissipation is an important parameter. Power consumption and dissipation or generations of more heat possess a restriction in the direction of the integration of more transistors. Several methods have been proposed to reduce power dissipation from system level to device level. Subthreshold circuits are widely used in more advanced applications due to ultra low-power consumption. The present work targets on construction of linear feedback shift registers (LFSR) in weak inversion region and their performance observed in terms of parameters like power delay product (PDP). In CMOS circuits subthreshold region of operation allows a low-power for ample utilizations but this advantage get with the penalty of flat speed. For the entrenched and high speed applications, improving the speed of subthreshold designs is essential. To enhance this, operate the devices at maximum current over capacitance. LFSR architectures build with various types of D flip flop and XOR gate circuits are analyzed. Circuit level Simulation is carried out using 130 nm technologies.

scholarly journals A low power comparator utilizing MTSCStack, DTTS, and bulk-driven techniques

2021 ◽  
Vol 10 (3) ◽  
pp. 221
Author(s):  
Mohd Tafir Mustaffa
Keyword(s):  
Low Power ◽  
High Speed ◽  
Low Voltage ◽  
Promising Result ◽  
Industrial Applications ◽  
Modern Technology ◽  
Total Power ◽  
Cmos Process ◽  
Process Technology ◽  
Differential Pair

Comparator is one of the main blocks that play a vital task in the performance of analog to digital converters (ADC) in all modern technology devices. High-speed devices with low voltage and low power are considered essential for industrial applications. The design of a low-power comparator with high speed is required to accomplish the requirements mostly in electronic devices that are necessary for high-speed ADCs. However, a high-speed device that leads the scaling down of CMOS process technology will consume more power. Thus, power reduction techniques such as multi-threshold super cut-off stack (MTSCStack), dual-threshold transistor stacking (DTTS), a bulk-driven, and a bulk-driven differential pair were studied in this work. This study aims to find and build the combination of these techniques to produce a comparator that can operate in low power without compromising existing performance using the 0.13-µm CMOS process. A comparator with a combination of MTSCStack, DTTS, and NMOS bulk-driven differential pair shows the most promising result of 6.29 µW for static power, 17.15 µW for dynamic power, and 23.44 µW for total power.

A HIGH-PRECISION ULTRA-LOW-POWER HYSTERETIC VOLTAGE DETECTOR USING CURRENT-BASED COMPARISON

2013 ◽  
Vol 22 (09) ◽  
pp. 1340005
Author(s):  
WEN-XIAO GU ◽  
MENG-LIAN ZHAO ◽  
XIAO-BO WU ◽  
MINGYANG CHEN ◽  
QING LIU
Keyword(s):  
Low Power ◽  
High Precision ◽  
Total Power ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Total Power Consumption ◽  
Harvesting Systems ◽  
Current Converter ◽  
Average Variation ◽  
A Current

This paper presented a high-precision, ultra-low-power hysteretic voltage detector (HVD) using current comparison to detect voltage default crossing moments for energy-harvesting systems (EHS) in wireless sensor network (WSN) applications. The HVD mainly consists of four parts: a specially designed voltage-to-current converter (VCC) with thermal stability improvement, a comparison core to make current-based comparison, a current pre-amplifier to improve its transient performance and a Schmitt inverter to provide the hysteresis characteristic. The prototype of this HVD has been implemented in SMIC 0.18 μm CMOS process and occupies 0.036 mm2 area without pads. The hysteresis window is about 120 mV wide. The temperature coefficient (TC) is about -170.2 ppm°C. The average variation to different process corners can be reduced to 1.4% by MOSFET and resistor trimming. The total power consumption is only 701.5 nW when VDD is around 1.8 V.

An Ultra-low Power, High SNM, High Speed and High Temperature of 6T-SRAM Cell in 3C-SiC 130 nm CMOS Technology

2020 ◽  
Vol 12 (4) ◽  
pp. 04024-1-04024-4
Author(s):  
D. Berbara ◽  
◽  
M. Abboun Abid ◽  
M. Hebali ◽  
M. Benzohra ◽  
...  
Keyword(s):  
High Temperature ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Ultra Low Power ◽  
Sram Cell
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