Design and Implementation of New Feynman and Toffoli (NFT) Gates in Quantum-dot Cellular Automata (QCA)

2017 ◽  
Vol 2 (4) ◽  
pp. 64-67
Author(s):  
Sajjad Waheed ◽  
Md. Golam Rasel
Keyword(s):  
Information Processing ◽  
Power Consumption ◽  
Low Power ◽  
Processing System ◽  
Logic Gates ◽  
Cmos Technology ◽  
Low Power Consumption ◽  
Switching Frequency ◽  
Promising Alternative ◽  
Scale Integration

In this paper, New Feynman and Toffoli (NFT) gate is proposed based on QCA logic gates. The proposed circuit is a promising future in constructing of nano-scale low power consumption information processing system and can stimulate higher digital applications in QCA. QCA technology is a promising alternative to CMOS technology. It is attractive due to its fast speed, small area and low power consumption. A novel electronics paradigm for information processing and communication by QCA offers technology. QCA technology has the potential for attractive features such as faster speed, higher scale integration, higher switching frequency, smaller size and low power consumption than transistor based technology.

scholarly journals A Novel Design and Implementation of New Double Feynman and Six-correction logic (DFSCL) gates in Quantum-dot Cellular Automata (QCA)

2017 ◽  
Vol 13 (15) ◽  
pp. 265
Author(s):  
Sajjad Waheed ◽  
Sharmin Aktar ◽  
Ali Newaz Bahar
Keyword(s):  
Information Processing ◽  
Cellular Automata ◽  
Power Consumption ◽  
Low Power ◽  
Logic Gate ◽  
Processing System ◽  
Logic Gates ◽  
Low Power Consumption ◽  
Switching Frequency ◽  
Promising Alternative

In recent years, quantum cellular automata (QCA) have been used widely to digital circuits and systems. QCA technology is a promising alternative to CMOS technology. It is attractive due to its fast speed, small area and low power consumption. The QCA offers a novel electronics paradigm for information processing and communication. It has the potential for attractive features such as faster speed, higher scale integration, higher switching frequency, smaller size and low power consumption than transistor based technology. In this paper, Double Feynman and Six-correction logic gate (DFSCL) is proposed based on QCA logic gates: MV gate and Inverter gate. The proposed circuit is a promising future in constructing of nano-scale low power consumption information processing system and can stimulate higher digital applications in QCA.

scholarly journals All-solid-state Ion Synaptic Transistor for Wafer-scale Integration with Electrolyte of a Nanoscale Thickness

2020 ◽  
Author(s):  
Ji-Man Yu ◽  
Chungryeol Lee ◽  
Da-Jin Kim ◽  
Hongkeun Park ◽  
Joon-Kyu Han ◽  
...  
Keyword(s):  
Solid State ◽  
Power Consumption ◽  
Low Power ◽  
Recognition Rate ◽  
Chemical Vapor ◽  
Low Power Consumption ◽  
Promising Alternative ◽  
Von Neumann ◽  
Neuromorphic Hardware ◽  
Scale Integration

Abstract Neuromorphic hardware computing is a promising alternative to von Neumann computing by virtue of its parallel computation, and low power consumption. To implement neuromorphic hardware based on deep neural network (DNN), a number of synaptic devices should be interconnected with neuron devices. For ideal hardware DNN, not only scalability and low power consumption, but also a linear and symmetric conductance change with the large number of conductance levels are required. Here an all-solid-state polymer electrolyte-gated synaptic transistor (pEGST) was fabricated on an entire silicon wafer with CMOS microfabrication and initiated chemical vapor deposition (iCVD) process. The pEGST showed good linearity as well as symmetry in potentiation and depression, conductance levels up to 8,192, and low switching energy smaller than 20 fJ/pulse. Selected 128 levels from 8,192 used to identify handwritten digits in the MNIST database with the aid of a multilayer perceptron, resulting in a recognition rate of 91.7 %.

scholarly journals A Novel Design and Implementation of 8-3 Encoder Using Quantum-dot Cellular Automata (QCA) Technology

2017 ◽  
Vol 13 (15) ◽  
pp. 254
Author(s):  
Md. Sofeoul-Al-Mamun ◽  
Mohammad Badrul Alam Miah ◽  
Fuyad Al Masud
Keyword(s):  
Information Processing ◽  
Cellular Automata ◽  
Quantum Dot ◽  
Processing System ◽  
Logic Gates ◽  
Oxide Semiconductor ◽  
Switching Frequency ◽  
Promising Alternative ◽  
Quantum Dot Cellular Automata ◽  
Or Gate

In recent years Quantum-dot Cellular Automata (QCA) has been considered one of the emerging nano-technology for future generation digital circuits and systems. QCA technology is a promising alternative to Complementary Metal Oxide Semiconductor (CMOS) technology. Thus, QCA offers a novel electronics paradigm for information processing and communication system. It has attractive features such as faster speed, higher scale integration, higher switching frequency, smaller size and low power consumption compared to the transistor based technology. It is projected as a promising nanotechnology for future Integrated Circuits (ICs). A quantum dot cellular automaton complex gate is composed from simple 3-input majority gate. In this paper, a 8-3 encoder circuit is proposed based on QCA logic gates: the 4-input Majority Voter (MV) OR gate. This 7-input gate can be configured into many useful gate structures such as a 4-input AND gate, a 4-input OR gate, 2-input AND and 2-input OR gates, 2-input complex gates, multi-input complex gates. The proposed circuit has a promising future in the area of nano-computing information processing system and can be stimulated with higher digital applications in QCA.

A Quantitative Approach of Reversible Logic Gates in QCA

2015 ◽  
Vol 3 ◽  
pp. 22 ◽  
Author(s):  
Abdullah Al Shafi ◽  
Ali Newaz Bahar ◽  
Md Shifatul Islam
Keyword(s):  
Low Power ◽  
Vlsi Design ◽  
Processing System ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Cmos Technology ◽  
Reversible Logic ◽  
Oxide Semiconductor ◽  
Switching Frequency

Abstract—Quantum Dot Cellular Automata (QCA) is an eminent nano-technology and solution of Complementary Metal Oxide Semiconductor (CMOS) for it’s computation and transformation procedure. It is attractive for it’s size, faster speed, high scalable feature, low power consumption and higher switching frequency compared to CMOS technology. Reversible logic has many factual operation in QCA as well as VLSI design, nanotechnology, digital signal processing (DSP). This paper presents a systematic design of reversible gate based on QCA. A modified pattern of Fredkin gate, MCL gate and a new scheme of URG gate, BJN gate is proposed in this paper. For design and verification QCADesigner, a widely used simulation tool is employed. The proposed circuits can be used in erecting of nano scale low power information processing system and modelingcomplex computing systems.

Design of ultra compact all-optical XOR and AND logic gates with low power consumption

2011 ◽  
Vol 284 (14) ◽  
pp. 3528-3533 ◽  
Author(s):  
Yuhei Ishizaka ◽  
Yuki Kawaguchi ◽  
Kunimasa Saitoh ◽  
Masanori Koshiba
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Logic Gates ◽  
Low Power Consumption ◽  
All Optical

A Low Power Design of SM4 Cipher Based on MUX S-Box Architecture

2013 ◽  
Vol 411-414 ◽  
pp. 125-130
Author(s):  
Yan Bo Niu ◽  
An Ping Jiang
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Data Transmission ◽  
Block Cipher ◽  
Low Power Design ◽  
Cmos Technology ◽  
Smart Cards ◽  
Low Power Consumption

SM4 is a 128-bit block cipher used in SOC and smart cards to ensure the safety of data transmission. In order to realize a low power implementation of the SM4 cipher block, some S-boxes were evaluated firstly and we proposed a new architecture of SM4 S-box called MUX S-box with a power consumption of 13.92W@10Mhz on SMIC 0.18m technology, Meanwhile, the implementation of SM4 cipher round based on the SM4 MUX S-box was completed and a low power consumption of 0.33mW @ 10 MHz on 0.18 m CMOS technology is achieved.

scholarly journals Silicon nanomembrane phototransistor flipped with multifunctional sensors toward smart digital dust

2020 ◽  
Vol 6 (18) ◽  
pp. eaaz6511 ◽  
Author(s):  
Gongjin Li ◽  
Zhe Ma ◽  
Chunyu You ◽  
Gaoshan Huang ◽  
Enming Song ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Flexible Electronics ◽  
Large Scale ◽  
Cmos Technology ◽  
Low Power Consumption ◽  
Stimuli Responsive ◽  
Single Chip ◽  
Detection Mechanism ◽  
Silicon Nanomembrane

The sensing module that converts physical or chemical stimuli into electrical signals is the core of future smart electronics in the post-Moore era. Challenges lie in the realization and integration of different detecting functions on a single chip. We propose a new design of on-chip construction for low-power consumption sensor, which is based on the optoelectronic detection mechanism with external stimuli and compatible with CMOS technology. A combination of flipped silicon nanomembrane phototransistors and stimuli-responsive materials presents low-power consumption (CMOS level) and demonstrates great functional expansibility of sensing targets, e.g., hydrogen concentration and relative humidity. With a device-first, wafer-compatible process introduced for large-scale silicon flexible electronics, our work shows great potential in the development of flexible and integrated smart sensing systems for the realization of Internet of Things applications.

scholarly journals An efficient high speed, high frequency domino-logic based circuit

2018 ◽  
Vol 7 (2) ◽  
pp. 252
Author(s):  
Mahdi Zare ◽  
Hossein Manouchehrpour ◽  
Ahmad Esmaeilkhah
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Frequency ◽  
High Speed ◽  
Large Scale ◽  
Considerable Improvement ◽  
Low Power Consumption ◽  
Domino Logic ◽  
Large Scale Integration ◽  
Scale Integration

As the Very Large-Scale Integration (VLSI) techniques are mostly focused on high-speed and low power consumption circuits, various techniques and technologies were investigated to gain these two precious goals. Domino-logic is one of the circuits which is regarded to have high speed, high frequency and low power consumption. This work proposes a Domini logic circuit which has improved PDP compare to the previous one. The suggested circuit was simulated and the attained results show a considerable improvement in circuit’s speed in respect with its ancestor. The PDP of the circuit in 90 nm, biased at 1V, has been calculated as 53% approximately improvement. This improvement for PDP in 65 nm, 45 nm and 32 nm are 48%, 47% and 51% respectively.  

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