CU Core Column Enables Fine Pitch & High-Density 3D Packaging

This paper highlights the possible combination of technologies such as thick film screen printing, ink jet, and post-firing thin film processes in conjunction with laser-drilled fine vias to produce high-density, miniaturized LTCC substrates. To obtain the silver pattern on the inner layers, both conventional thick film printing and ink jet printing (using nano silver particle dispersed ink) were applied on the ceramic green sheets. The ink jet process made it possible to metallize fine lines with line/space = 30/30 μm. For interlayer connections, fine vias of 30 μm in diameter formed by UV laser were used. Then these sheets were stacked on top of each other and fired to obtain a base substrate. On this base substrate, fine copper patterns for flip chip mounting were formed by a thin film process. The surface finish consisted of a nickel passivation and a gold layer deposited by electroless plating. The combination of the three patterning processes for conducting traces and UV laser drilling of fine vias make it appear possible to realize fine pitch LTCC, for example, for flip chip device mounting.

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Die to Die and Die To Wafer Bonding Solution for High Density, Fine Pitch Micro-Bumped Die

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2012dpc-tha15 ◽

2012 ◽

Vol 2012 (DPC) ◽

pp. 002251-002284 ◽

Cited By ~ 1

Author(s):

Gilbert Lecarpentier ◽

Joeri De Vos

Keyword(s):

Wafer Bonding ◽

Flip Chip ◽

High Accuracy ◽

High Density ◽

Size Reduction ◽

Direct Impact ◽

3 Dimensional ◽

Fine Pitch ◽

Placement Accuracy ◽

Die Bonding

Higher density interconnection using 3-Dimensional technology implies a pitch reduction and the use of micro-bumps. The micro-bump size reduction has a direct impact on the placement accuracy needed on the die placement and flip chip bonding equipment. The paper presents a Die-to-Die and Die-to-Wafer, high accuracy, die bonding solution illustrated by the flip chip assembly of a large 2x2cm die consisting of 1 million 10 μm micro-bumps at 20 μm pitch

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Bonding Technologies for 3D integration

International Symposium on Microelectronics ◽

10.4071/isom-2015-wa24 ◽

2015 ◽

Vol 2015 (1) ◽

pp. 000231-000234

Author(s):

Sascha Lohse ◽

Alexander Wollanke

Keyword(s):

Flip Chip ◽

Process Technology ◽

3D Integration ◽

Test Procedures ◽

Fine Pitch ◽

Ic Packaging ◽

Die Stacking ◽

3D Packaging ◽

Small Bump ◽

Suitable Process

Tougher requirements related to the request for smaller, lighter and multi-functional electronic devices impose increased demands on IC packaging. Ever more complex circuitry, fine pitch and micro bump designs and die stacking are examples of how the industry meets these demands. Finding a suitable process technology for 3D packaging can be a challenge. This paper provides information about various connection methods predominantly used in today's 3D packaging. In comprehensive trials, various dies characterized by high bump count (up to 143,000), fine pitch (down to 25 μm) and small bump diameter (down to 13 μm) were placed on a substrate using a semi-automated flip chip bonder. This whitepaper describes test procedures for different 3D integration technologies and presents utilized process parameters and results.

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The Die Embedded and RDL structure on the high density substrate (i-THOP®) for mobile application

International Symposium on Microelectronics ◽

10.4071/isom-2016-tp11 ◽

2016 ◽

Vol 2016 (1) ◽

pp. 000001-000006

Author(s):

Masahiro Kyozuka ◽

Tatsuro Yoshida ◽

Noriyoshi Shimizu ◽

Koichi Tanaka ◽

Tetsuya Koyama

Keyword(s):

Mobile Devices ◽

Manufacturing Process ◽

Printed Circuit Board ◽

Semiconductor Device ◽

Current Trend ◽

High Density ◽

Circuit Board ◽

Fine Pitch ◽

Package Size ◽

Proper Material

Abstract The current trend in the electronics industry is one of increased computing performance, combined with a seemingly unending demand for portability and increased miniaturization; this is especially evident in the significant changes to the semiconductor device. To sustain the performance-improvement trend without increasing total cost, the partitioning of single die into a multi-chip architecture is widely studied in industry. These partitioned chips are then integrated into a single system-in-package (SiP). However, partitioning a single die into multiple split die causes two major challenges. The first is that it creates the need for very high density die to die interconnection. This interconnection is needed to provide enough routing density between the multiple die. Based on design studies, it believes that 2μm line and 2μm space is required in the package substrate. The second challenge is created by the increase in the overall die size. After partitioning the single die, each resulting smaller die must have its own I/O circuits, and effectively increases the total die area. This increase is a penalty, as mobile devices have a limited package size. When comparing a conventional package on package (PoP), the SiP requires a higher pin count with a finer pitch connection between the die and the memory. This finer pitch is needed to have enough I/Os, but within a limited package size to support mobile devices. To overcome these challenges, the structure of i-THOP® with POP pad, named “i-THOP® with Die embedded +ReDestribution Layer(RDL) structure”, has been developed. Herein, i-THOP® (integrated Thin film High density Organic Package) is a type of high-density substrate A key aspect to development of Die embedded +RDL is forming the multiple redistribution layers (RDL) over die and the fine pitch via connection. To achieve this, the proper material set was selected based on stress simulations and basic experiments. Regarding the manufacturing process, a conventional printed-circuit board (PCB) production line was used to minimize production cost. This article reports the manufacturing process and characteristics of the structure.

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Si Vapor Chamber Integrated with Through Silicon Via for 3D Packaging

International Symposium on Microelectronics ◽

10.4071/isom-2013-wa51 ◽

2013 ◽

Vol 2013 (1) ◽

pp. 000552-000557 ◽

Cited By ~ 1

Author(s):

Jun Taniguchi ◽

Takeshi Shioga ◽

Yoshihiro Mizuno

Keyword(s):

Thermal Resistance ◽

Heat Dissipation ◽

Working Fluid ◽

In Situ Observation ◽

Vapor Chamber ◽

Cover Glass ◽

Through Silicon Via ◽

Improvement Rate ◽

Fine Pitch ◽

3D Packaging

We demonstrate an etched silicon vapor chamber integrated with a through-silicon via (TSV) for 3D packaging. The Si vapor chamber chip enables low mismatch in the thermal expansion coefficient of a Si-LSI chip and provides a new heat dissipation path for 3D-LSI inter layer cooling. For the first prototype of the vapor chamber, an outside 33-mm × 33-mm chip consisting of a 25-mm × 25-mm area for the vapor chamber, a wick structure 30-μm high, and a vapor passage 100-μm high is developed. In-situ observation of the behavior of the working fluid through the cover glass and heat transfer enhancement is successfully demonstrated. The improvement rate of thermal resistance is 7.1% compared to a test chip without working fluid. Next, the fluid flow of a second vapor chamber prototype consisting of the first prototype integrated with a TSV structure using a Si pillar of 150-μm diameter is investigated. Thermal resistance and droplet observation conducted to evaluate the influence of the TSV. The operation of the vapor chamber is confirmed when a Si pillar is arranged to a coarse pitch of more than 500 μm. A droplet is generated and the vapor passage is partially obstructed. However, the droplet eventually degenerated and the performance of the vapor chamber is maintained. When the Si pillar is arranged to a fine pitch of 200 μm, the entire vapor passage is blocked during the liquid charging process, and no improvement is observed in the thermal resistance of the chip.

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Wafer Level Assembly Technique Development for Fine Pitch Flip Chip 3D Die-to-Wafer Integration

International Symposium on Microelectronics ◽

10.4071/isom-2010-wp1-paper3 ◽

2010 ◽

Vol 2010 (1) ◽

pp. 000548-000553

Author(s):

Zhaozhi Li ◽

Brian J. Lewis ◽

Paul N. Houston ◽

Daniel F. Baldwin ◽

Eugene A. Stout ◽

...

Keyword(s):

Flip Chip ◽

Low Cost ◽

Three Dimensional ◽

Cost Effective ◽

Market Demand ◽

Wafer Level ◽

Packaging Technology ◽

Fine Pitch ◽

3D Packaging ◽

Assembly Technique

Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced. Research efforts were focused on the high-density flip chip wafer level assembly techniques, as well as the challenges, innovations and solutions associated with this type of 3D packaging technology. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; wafer level flip chip assembly program creation and yield improvements; and set up of the Pb-free reflow profile for the assembled wafer. 100% yield was achieved on the test vehicle wafer that has totally 1,876 flip chip dies assembled on it. This work has demonstrated that the flip chip 3D die-to-wafer packaging architecture can be processed with robust yield and high manufacturing throughput, and thus to be a cost effective, rapid time to market alternative to emerging 3D wafer level integration methodologies.

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