scholarly journals An Optimized CB-UT Multiplier for Efficient Design of the AM Operator

2020 ◽  
Author(s):  
Hari Krishna Modalavalasa
Keyword(s):  
Signal Processing ◽  
Performance Optimization ◽  
High Speed ◽  
High Performance ◽  
New Technology ◽  
Digital Signal ◽  
Propagation Delay ◽  
Efficient Design ◽  
Silicon Area ◽  
Low Area

The multiplication and accumulation are the vital operations involved in almost all the Digital Signal Processing applications. With the advent of new technology in the domain of VLSI, communication and signal processing, there is an ever going demand for the high speed processing and low area design. In today's technology, Add-Multiply (AM) operator or Multiply Accumulator (MAC) units are generally employed in all high performance digital signal processors (DSP) and controllers. The performance of AM operator mainly depends on the speed of multiplier. A lot of research has been contributed in this area and the conventional multipliers were modified to provide good speed performance but needs to be improved further along with area optimization. Urdhwa-Tiryakbhyam Multiplier (UTM) architecture is adopted from ancient Indian mathematics "Vedas’ and can generate the partial products and sums in one step, which reduces the carry propagation from LSB to MSB. UTM can be used to implement high performance AM operators but results in larger silicon areas. This increased area can be minimized by using the modified compressor based design of UTM. In this work, the carrylook-ahead (CLA) adder is adopted instead of parallel adders for high speed of accumulation. So, the Compressor-Based-Urdhwa-Tiryakbhyam (CB-UT) multiplier with CLA results in both area and performance optimization of Add-Multiply operator. The functionality of this architecture is evaluated by comparing with the Modified Booth (MB) multiplier based AM operator in terms of performance parameters like propagation delay, power consumption and silicon-area. The design is implemented and verified using Xilinx Spartan-3E FPGA and ISE Simulator.

Low-Power and Area-Efficient Parallel Multiplier Design Using Two-Dimensional Bypassing

2016 ◽  
Vol 26 (02) ◽  
pp. 1750030 ◽  
Author(s):  
Pankaj Kumar ◽  
Rajender Kumar Sharma
Keyword(s):  
Signal Processing ◽  
Low Power ◽  
High Speed ◽  
Digital Signal ◽  
Cmos Technology ◽  
Two Dimensional ◽  
Efficient Design ◽  
Parallel Multiplier ◽  
Power Delay Product ◽  
Area Efficient

To develop low-power, high-speed and area-efficient design for portable electronics devices and signal processing applications is a very challenging task. Multiplier has an important role in digital signal processing. Reducing the power consumption of multiplier will bring significant power reduction and other associated advantages in the overall digital system. In this paper, a low-power and area-efficient two-dimensional bypassing multiplier is presented. In two-dimensional bypassing, row and column are bypassed and thus the switching power is saved. Simulation results are realized using UMC 90[Formula: see text]nm CMOS technology and 0.9[Formula: see text]V, with Cadence Spectre simulation tool. The proposed architecture is compared with the existing multiplier architectures, i.e., Braun’s multiplier, row bypassing multiplier, column bypassing multiplier and row and column bypassing multiplier. Performance parameters of the proposed multiplier are better than the existing multipliers in terms of area occupation, power dissipation and power-delay product. These results are obtained for randomly generated input test patterns having uniform distribution probability.

Design of Universal Signal Processing Machine Based on Multiple DSP

2013 ◽  
Vol 321-324 ◽  
pp. 1241-1244
Author(s):  
Yang Jian ◽  
Yu Hao Liu ◽  
Xi Jing Zhao ◽  
Hao Ming Chen
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
High Speed ◽  
High Performance ◽  
Digital Signal ◽  
Multiple Channel ◽  
Processing Machine ◽  
Large Memory ◽  
High Speed Data ◽  
Board Level

With the development and application of technique on high speed digital signal processing, wide bandwidth processing, high-speed data exchanging and flexible interlink structure have been the developing trend of modern high performance signal processing machine. In this paper, one universal signal processing machine is designed based on six pieces of ADSP-TS201 TigerSHARC processors, which owns good characteristics such as: large memory, excellent processing and data-exchanging performance, reconstitution, good expansibility. This signal processing machine adopts 64Bit, 66MHz CPCI bus standard and supports the function of extending processing performance by interlinking multiple boards. The high-speed data-exchanging is realized with multiple channel optical fiber. Furthermore, it owns board-level BIT function.

scholarly journals Introduction to the Special Issue on Digital Signal Processing in Radio Astronomy

2016 ◽  
Vol 05 (04) ◽  
pp. 1602002 ◽  
Author(s):  
D. C. Price ◽  
J. Kocz ◽  
M. Bailes ◽  
L. J. Greenhill
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Radio Astronomy ◽  
Graphics Processing Units ◽  
High Speed ◽  
High Performance ◽  
Digital Signal ◽  
General Purpose ◽  
Special Issue ◽  
Dsp Systems

Advances in astronomy are intimately linked to advances in digital signal processing (DSP). This special issue is focused upon advances in DSP within radio astronomy. The trend within that community is to use off-the-shelf digital hardware where possible and leverage advances in high performance computing. In particular, graphics processing units (GPUs) and field programmable gate arrays (FPGAs) are being used in place of application-specific circuits (ASICs); high-speed Ethernet and Infiniband are being used for interconnect in place of custom backplanes. Further, to lower hurdles in digital engineering, communities have designed and released general-purpose FPGA-based DSP systems, such as the CASPER ROACH board, ASTRON Uniboard, and CSIRO Redback board. In this introductory paper, we give a brief historical overview, a summary of recent trends, and provide an outlook on future directions.

scholarly journals Design of High Speed and Low Area Confined Multiplier on FPGA

2021 ◽  
Vol 11 (4) ◽  
pp. 2736-2746
Author(s):  
Kandagatla Ravi Kumar ◽  
Cheeli Priyadarshini ◽  
Kanakam Bhavani ◽  
Ankam Varun Sundar Kumar ◽  
Palanki Naga Nanda Sai
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Digital Signal ◽  
Low Area ◽  
Field Programmable ◽  
Dsp Applications ◽  
Advanced Applications ◽  
Main Factor

In this Advanced world, Technology is playing the major role. Most importantly development in Electronics field has a large impact on the improved life style. Among the advanced applications, DSP ranks first in place. Multipliers are the most basic elements that are widely used in the Digital Signal Processing (DSP) applications. Therefore, the design of the multiplier is the main factor for the performance of the device. Using RTL simulation and a Field Programmable Gate Array (FPGA), we compare the performance of a serial multiplier with an advanced multiplier. Many single bit adders are removed and replaced with multiplexers in this project. So that the less often used FPGAs are fully used by occupying fewer divisions and slices. The use of multiplier architecture results in significant reductions in FPGA resources, latency, area, and power. These multiplication approaches are created utilizing RTL simulation in Xilinx ISE simulator and synthesis in Xilinx ISE 14.7. Finally, the Spartan 3E FPGA is used to implement the design.

scholarly journals High Speed, Low Area Exact Speculative Carry Look Ahead Adder using MGDI Technique

2019 ◽  
Vol 8 (6) ◽  
pp. 5090-5094
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
High Speed ◽  
Digital Signal ◽  
Propagation Delay ◽  
Vital Role ◽  
Switching Behavior ◽  
Low Area ◽  
Look Ahead ◽  
Heating Up

The Exact Speculative Carry Look Ahead Adder using the Modified-GDI (Modified-Gate Diffusion Input) is suggested in this work. The delay, area and power tradeoff plays a vital role in VLSI. We already know that designs which are of CMOS style occupy more space may consume more power consumption. The switching behavior of the circuit cause the heating up of integrated circuits affects the working conditions of the functional unit. The adders are the main parts of several applications such as microprocessors, microcontrollers and digital signal processors and also in real time applications. Hence it is important to minimize the adder blocks to design a perfect processor. This work is proposed on a 16 bit carry look ahead adder is designed by using MGDI gate and 4T XOR gates and a speculator blocks. The proposed MGDI carry Look Ahead adder occupies 68% less area and the power consumption and the propagation delay also drastically reduces when compared to the conventional carry Look Ahead adder why because the number transistors drastically reduces from 1448 (Conventional) to 456 (Proposed CLA). The simulation results of the proposed design implemented in Xilinx.

scholarly journals Design and Analysis of Multiplier Using High Speed Adders

2021 ◽  
pp. 68-75
Author(s):  
Swetha R ◽  
Priyanka M ◽  
Suvetha S ◽  
Kavitha S
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
Digital Filters ◽  
Digital Signal ◽  
Propagation Delay ◽  
Digital Systems ◽  
Operating Speed ◽  
Look Ahead ◽  
Dsp Applications ◽  
Multiplier Circuit

In all digital signal processing (DSP) applications like FFT, digital filters the main problem faced by processor is its propagation delay. Every high speed signal processing is depends on multiplier circuits. Multiplier performance is directly influenced by the adder design. In this paper, we design low power and high speed carry look ahead (CLA) adder for multiplier circuit by using multi value logic (MVL) based on quaternary signed digits (QSD). The ability of multi value logic (MVL) circuits to achieve more information density and high operating speed when compared to that of existing binary circuits is highly impressive. MVL circuits have attracted important attention for the design of digital systems. Based on quaternary signed digits, the carry look ahead adder is designed, implemented in multiplier circuit and simulated by using cadence virtuoso design suite by 180nF technology.

scholarly journals An efficient hardware logarithm generator with modified quasi-symmetrical approach for digital signal processing

2020 ◽  
Vol 10 (5) ◽  
pp. 4671
Author(s):  
Minh-Hong Nguyen
Keyword(s):  
Signal Processing ◽  
Error Analysis ◽  
Digital Signal Processing ◽  
Real Time ◽  
High Speed ◽  
Hardware Implementation ◽  
Approximation Error ◽  
Digital Signal ◽  
Traditional Methods ◽  
Low Area

This paper presents a low-error, low-area FPGA-based hardware logarithm generator for digital signal processing systems which require high-speed, real time logarithm operations. The proposed logarithm generator employs the modified quasi-symmetrical approach for an efficient hardware implementation. The error analysis and implementation results are also presented and discussed. The achieved results show that the proposed approach can reduce the approximation error and hardware area compared with traditional methods.

Method of estimation of hidden correlation of narrowband noise signals

2019 ◽  
pp. 34-39 ◽  
Author(s):  
E.I. Chernov ◽  
N.E. Sobolev ◽  
A.A. Bondarchuk ◽  
L.E. Aristarhova
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
New Technology ◽  
Digital Signal ◽  
Measuring Instruments ◽  
Central Frequency ◽  
Pearson Criterion ◽  
Useful Signal ◽  
Band Limited ◽  
Narrowband Noise

The concept of hidden correlation of noise signals is introduced. The existence of a hidden correlation between narrowband noise signals isolated simultaneously from broadband band-limited noise is theoretically proved. A method for estimating the latent correlation of narrowband noise signals has been developed and experimentally investigated. As a result of the experiment, where a time frag ent of band-limited noise, the basis of which is shot noise, is used as the studied signal, it is established: when applying the Pearson criterion, there is practically no correlation between the signal at the Central frequency and the sum of signals at mirror frequencies; when applying the proposed method for the analysis of the same signals, a strong hidden correlation is found. The proposed method is useful for researchers, engineers and metrologists engaged in digital signal processing, as well as developers of measuring instruments using a new technology for isolating a useful signal from noise – the method of mirror noise images.

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