scholarly journals High Speed, Low Area Exact Speculative Carry Look Ahead Adder using MGDI Technique

2019 ◽  
Vol 8 (6) ◽  
pp. 5090-5094
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
High Speed ◽  
Digital Signal ◽  
Propagation Delay ◽  
Vital Role ◽  
Switching Behavior ◽  
Low Area ◽  
Look Ahead ◽  
Heating Up

The Exact Speculative Carry Look Ahead Adder using the Modified-GDI (Modified-Gate Diffusion Input) is suggested in this work. The delay, area and power tradeoff plays a vital role in VLSI. We already know that designs which are of CMOS style occupy more space may consume more power consumption. The switching behavior of the circuit cause the heating up of integrated circuits affects the working conditions of the functional unit. The adders are the main parts of several applications such as microprocessors, microcontrollers and digital signal processors and also in real time applications. Hence it is important to minimize the adder blocks to design a perfect processor. This work is proposed on a 16 bit carry look ahead adder is designed by using MGDI gate and 4T XOR gates and a speculator blocks. The proposed MGDI carry Look Ahead adder occupies 68% less area and the power consumption and the propagation delay also drastically reduces when compared to the conventional carry Look Ahead adder why because the number transistors drastically reduces from 1448 (Conventional) to 456 (Proposed CLA). The simulation results of the proposed design implemented in Xilinx.

scholarly journals Power Efficient Clock Distribuition for Switched Capacitor DC-DC Converters

2018 ◽  
Vol 10 (1) ◽  
pp. 27
Author(s):  
A. S. R. Murthy ◽  
Sridhar T.
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
Power Distribution ◽  
High Speed ◽  
Low Voltage ◽  
Data Communication ◽  
Distribution Networks ◽  
Propagation Delay ◽  
Switched Capacitor ◽  
Power Efficient

<p>In various VLSI based digital systems, on-chip interconnects have become the system bottleneck in state-of-the-art chips, limiting the performance of high-speed clock distributions and data communication devices in terms of propagation delay and power consumption. Increasing power requirements and power distribution to multi-core architectures is also posing a challenge to power distribution networks in the integrated circuits. Clock distribution networks for the switched capacitor converters becomes a non-trivial task and the increased interconnect lengths cause clock degradation and power dissipation. Therefore, this paper introduce low swing signaling schemes to decrease delay and power consumption. A comparative study presented of low voltage signaling schemes in terms of delay, power consumption and power delay product. Here, we have presented a power efficient signaling topology for driving the clocks to higher interconnect lengths.</p>

scholarly journals An Optimized CB-UT Multiplier for Efficient Design of the AM Operator

2020 ◽  
Author(s):  
Hari Krishna Modalavalasa
Keyword(s):  
Signal Processing ◽  
Performance Optimization ◽  
High Speed ◽  
High Performance ◽  
New Technology ◽  
Digital Signal ◽  
Propagation Delay ◽  
Efficient Design ◽  
Silicon Area ◽  
Low Area

The multiplication and accumulation are the vital operations involved in almost all the Digital Signal Processing applications. With the advent of new technology in the domain of VLSI, communication and signal processing, there is an ever going demand for the high speed processing and low area design. In today's technology, Add-Multiply (AM) operator or Multiply Accumulator (MAC) units are generally employed in all high performance digital signal processors (DSP) and controllers. The performance of AM operator mainly depends on the speed of multiplier. A lot of research has been contributed in this area and the conventional multipliers were modified to provide good speed performance but needs to be improved further along with area optimization. Urdhwa-Tiryakbhyam Multiplier (UTM) architecture is adopted from ancient Indian mathematics "Vedas’ and can generate the partial products and sums in one step, which reduces the carry propagation from LSB to MSB. UTM can be used to implement high performance AM operators but results in larger silicon areas. This increased area can be minimized by using the modified compressor based design of UTM. In this work, the carrylook-ahead (CLA) adder is adopted instead of parallel adders for high speed of accumulation. So, the Compressor-Based-Urdhwa-Tiryakbhyam (CB-UT) multiplier with CLA results in both area and performance optimization of Add-Multiply operator. The functionality of this architecture is evaluated by comparing with the Modified Booth (MB) multiplier based AM operator in terms of performance parameters like propagation delay, power consumption and silicon-area. The design is implemented and verified using Xilinx Spartan-3E FPGA and ISE Simulator.

scholarly journals Design of High-Speed Low Power Computational Blocks for DSP Processors

2021 ◽  
Vol 11 (2) ◽  
pp. 1419-1429
Author(s):  
Alivelu Manga N.
Keyword(s):  
Signal Processing ◽  
Integrated Circuits ◽  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Large Scale ◽  
Power Optimization ◽  
Digital Signal ◽  
Oxide Semiconductor ◽  
Performance Criteria

In today’s deep submicron VLSI (Very Large-Scale Integration) Integrated Circuits, power optimization and speed play a very important role. This importance for low power has initiated the designs where power dissipation is equally important as performance and area. Power reduction and power management are the key challenges in the design of circuits down to 100nm. For power optimization, there are several techniques and extension designs are applied in the literature. In real time Digital Signal Processing applications, multiplication and accumulation are significant operations. The primary performance criteria for these signal processing operations are speed and power consumption. To lower the power consumption, there are techniques like Multi threshold (Multi-Vth), Dula-Vth etc. Among those, a technique known as GDI (Gate diffusion Input) is used which allows reduction in power, delay and area of digital circuits, while maintaining low complexity of logic design. In this paper, various signal processing blocks like parallel-prefix adder, Braun multiplier and a Barrel shifter are designed using GDI (Gate diffusion Input) technique and compared with conventional CMOS (Complementary Metal Oxide Semiconductor) based designs in terms of delay and speed. The designs are simulated using Cadence Virtuoso 45nm technology. The Simulation results shows that GDI based designs consume less power and delay also reduced compared to CMOS based designs.

scholarly journals Enhanced and Efficient Carry Select Adder with Minimal Delay

2021 ◽  
Author(s):  
G. Srividhya ◽  
T. Sivasakthi ◽  
R. Srivarshini ◽  
P. Varshaa ◽  
S. Vijayalakshmi
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Digital Signal ◽  
Propagation Delay ◽  
Digital Signal Processors ◽  
Digital World ◽  
Carry Select Adder ◽  
Image Processors ◽  
Improved Model ◽  
Signal Processors

In today’s digital world, Arithmetic computations have been evolved as a core factor in digital signal processors, micro-controllers, and systems using arithmetic and logical operations such as adders, multipliers, image processors, and signal processors. One of the elements that play an important role in performing arithmetic calculations is an adder. Among many adders, the Carry Select Adder produces less propagation delay. However, there may be an increased delay, power consumption, and area required in the case of a normal Carry Select Adder. To overcome the mentioned drawbacks, an improved model of Carry Select Adder has been designed that uses Binary to Excess – 1 Converter. Instead of using multiple blocks of Ripple Carry Adders (RCAs), it is efficient and effective if one of the blocks is replaced with Binary to Excess – 1 Converter. As a result, we can achieve a high speed adder with minimal delay, minimal power, and reduced area.

scholarly journals VLSI Architecture of High Performance Multiplier for High Speed Applications

2020 ◽  
Vol 9 (3) ◽  
pp. 442-445
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Vlsi Architecture ◽  
Digital Signal ◽  
Full Adder ◽  
Vital Role ◽  
Path Delay

In the application of digital signal process multipliers play a vital role. With advances in technology, several researchers have tried and try to design multipliers which supply high speed, low power consumption, regularity of layout and thus less space or maybe combination of them in one multiplier factor. Thus, Compact VLSI design for four bit multiplier factor is planned during this paper that is appropriate for low power and high speed applications. Multiplier factor with high performance is achieved through the novel style of hybrid single bit full adder and Dadda algorithmic rule. The important path delay and power consumption of the planned multiplier factor square measure reduced by 65.9% and 24.5% severally when put next with existing multipliers. The planned multiplier factor is synthesized exploitation CADENCE five.1.0 EDA tool and simulated exploitation spectre virtuoso.

scholarly journals Design and Analysis of Multiplier Using High Speed Adders

2021 ◽  
pp. 68-75
Author(s):  
Swetha R ◽  
Priyanka M ◽  
Suvetha S ◽  
Kavitha S
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
Digital Filters ◽  
Digital Signal ◽  
Propagation Delay ◽  
Digital Systems ◽  
Operating Speed ◽  
Look Ahead ◽  
Dsp Applications ◽  
Multiplier Circuit

In all digital signal processing (DSP) applications like FFT, digital filters the main problem faced by processor is its propagation delay. Every high speed signal processing is depends on multiplier circuits. Multiplier performance is directly influenced by the adder design. In this paper, we design low power and high speed carry look ahead (CLA) adder for multiplier circuit by using multi value logic (MVL) based on quaternary signed digits (QSD). The ability of multi value logic (MVL) circuits to achieve more information density and high operating speed when compared to that of existing binary circuits is highly impressive. MVL circuits have attracted important attention for the design of digital systems. Based on quaternary signed digits, the carry look ahead adder is designed, implemented in multiplier circuit and simulated by using cadence virtuoso design suite by 180nF technology.

scholarly journals A Comparative Review on ALU using CMOS and GDI techniques for Power Dissipation and Propagation Delay

IJOSTHE ◽  
2020 ◽  
Vol 7 (1) ◽  
pp. 4
Author(s):  
Rimjhim Saxena ◽  
Kiran Sharma
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
High Speed ◽  
Digital Signal ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Compact Size ◽  
Comparative Review ◽  
Basic Functions ◽  
The One

Arithmetic and Logic Circuits are to be designed with less power, compact size, less propagation delay in this fast growing era of technology. Arithmetic operations are indispensable and the basic functions for any high speed low power applications like digital signal processing, microprocessors, image processing, etc. Consumption of power is the major issue in designing these circuits. Also the number of transistors required is also the one of the issues in designing the circuits. To minimize the transistors required in designing the circuits and to reduce the power consumption of the circuits, the authors have referred some techniques to overcome these problems in this paper. By reviewing all these techniques, the authors try to implement the GDI technique to reduce the power consumption and transistors count or the area required to design the circuits.

scholarly journals High Speed PSO Micro-Pipelined Adder

2020 ◽  
Vol 8 (5) ◽  
pp. 4073-4079
Keyword(s):  
Digital Signal Processor ◽  
Power Dissipation ◽  
High Speed ◽  
Continuous Monitoring ◽  
Digital Signal ◽  
Propagation Delay ◽  
Wearable Devices ◽  
Data Path ◽  
Processing Data ◽  
Cost Utilization

For continuous monitoring of individual wellbeing, wearable devices are indispensable. The limitations of cost, utilization of power, delay and restricted device measurements are the basic issues which should be dealt cautiously while designing these battery powered devices. The wearables use high-end processors dedicated for complicated signal processing. Data path plays a key role in every digital signal processor. Adder is the most widely used component in wearable technology. This work proposes a novel architecture for PS0 pipelined adder. The proposed adder is implemented in 65nm TSMC CMOS and its performance has been compared with state-of-art adders. The SPICE level simulations are performed on HSPICE using 65nm TSMC CMOS @ 1.2 V. All the designs have been simulated with extracted wire and layout parasitics. The proposed adder ensures the lowest propagation delay which is 79.33% less when compared to RCA and has a power dissipation of 0.225 mw which is 25.4 % less as compared to CLA. Besides, the proposed adder offers a benefit of having lower transistor count which is 49.6% less as compared to RCA.

scholarly journals Design and Analysis of 32-bit Reverse Converter based on low power Parallel Prefix Adder

2019 ◽  
Vol 9 (1) ◽  
pp. 3028-3031
Keyword(s):  
Low Power ◽  
High Speed ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
Propagation Delay ◽  
Main Role ◽  
Reverse Conversion ◽  
Reverse Converter ◽  
Parallel Prefix

The Residue Number System (RNS) based reverse converter can play as main role in Parallel arithmetic operations of Digital Signal Processing (DSP) applications and VLSI technologies. Normally, by the use of carry adders, the reverse conversion design gives high delay and high power consumption. Due to resolve of above problem, the design of reverse converter is proposed by the use of familiar high speed (less propagation delay) Parallel Prefix - Kogge Stone Adder (PP- KSA). This paper describes the design of 32-bit Reverse converter with regular PP-KSA and proposed MUX (Multiplex) logic of PP-KSA with Hybrid Modular Parallel Prefix structure (HMPE) separately. In addition to that, the performance of that designs are analysed based on area, delay and power independently. The Performance results of proposed MUX logic of PP-KSA Reverse converter design yields low power than the other design which uses the regular PP-KSA. The simulation and synthesis effects can be done in Xilinx ISE 14.2i tool.

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