scholarly journals Sub-Threshold Slope and ON/OFF Current variation in Nano-Scale MOSFETs

2019 ◽  
Author(s):  
Raja N Mir
Keyword(s):  
Three Dimensional ◽  
Device Performance ◽  
Gate Length ◽  
Subthreshold Slope ◽  
Current Ratio ◽  
Nano Scale ◽  
Current Variation ◽  
Mos Device ◽  
Three Dimensional Simulations

The Multi Gate transistors (MGT) have been used to improve the transistor device performance at the nanometer scales. MGTs alleviate many problems in the planar devices due to tighter control of the gate on the channel. In this paper the change in the Fin Architecture and Gate Length of the MOS device, is correlated with the Subthreshold Slope (SS) and ON/OFF current ratio. The study is done by conducting experiments and three-dimensional simulations.

scholarly journals Effect of Oxide Thickness on GaN-based Double Gate MOSFETs

2020 ◽  
Vol 16 (2) ◽  
Author(s):  
Safayet Ahmed ◽  
Md. Tanvir Hasan
Keyword(s):  
Oxide Thickness ◽  
Device Performance ◽  
Gate Length ◽  
Double Gate ◽  
Short Channel Effects ◽  
Subthreshold Slope ◽  
Short Channel ◽  
Power Switching ◽  
Switching Device ◽  
Channel Effects

The effect of oxide thickness (EOT) on GaN-based double gate (DG) MOSFETs have been explored for low power switching device. The gate length (LG) of 8 nm with 4 nm underlap is considered. The device is turned off and on for gate voltage (VGS) of 0 V and 1 V, respectively. The effective oxide thickness (EOT) is varied from 1 nm to 0.5 nm and the device performance is evaluated. For EOT = 0.5 nm, the OFF-state current (IOFF), subthreshold slope (SS) and drain induced barrier lowering (DIBL) are obtained 2.97×10-8 A/μm, 69.67 mV/dec and 21.753 mV/V, respectively. These results indicate that, it is possible to minimize short channel effects (SCEs) by using smaller value of EOT.

scholarly journals Circuit Analysis and Optimization of GAA Nanowire FET Towards Low Power and High Switching

2021 ◽  
Author(s):  
V. Bharath Sreenivas ◽  
Vadthiya Narendar
Keyword(s):  
Low Power ◽  
Circuit Analysis ◽  
Device Performance ◽  
Gate Length ◽  
Subthreshold Slope ◽  
Cmos Inverter ◽  
Spacer Length ◽  
Drain Side ◽  
Optimal Values ◽  
Simulation Results

Abstract The main aim of this work is to study the effect of symmetric and asymmetric spacer length variations towards source and drain on n-channel SOI JL vertically stacked (VS) nanowire (NW) FET at 10 nm gate length (LG). Spacer length is proved to be one of the stringent metrics in deciding device performance along with width, height and aspect ratio (AR). The physical variants in this work are symmetric spacer length (LSD), source side spacer length (LS) and drain side spacer length (LD). The simulation results give highest ION/IOFF ratio with LD variation compared to LS and LSD, whereas latter two variations have similar effect on ION/IOFF ratio. At 25 nm (2.5 × LG) of LD, the device gives appreciable ON current with the highest ION/IOFF ratio (2.19 × 108) with optimum subthreshold slope (SS) and ensures low power and high switching drivability. Moreover, it is noticed that among optimal values of LS and LD, the device ION/IOFF ratio has an improvement of 22.69% as compared to other variations. Moreover, the effect of various spacer dielectrics on optimized device is also investigated. Finally, the CMOS inverter circuit analysis is performed on the optimized symmetric and asymmetric spacer lengths.

scholarly journals Computational assessment of the influence of the overlap ratio on the power characteristics of a Classical Savonius wind turbine

2015 ◽  
Vol 5 (1) ◽  
Author(s):  
Konrad Kacprzak ◽  
Krzysztof Sobczak
Keyword(s):  
Experimental Data ◽  
Wind Turbine ◽  
Three Dimensional ◽  
Device Performance ◽  
Two Dimensional ◽  
Power Characteristics ◽  
Wide Range ◽  
Savonius Wind Turbine ◽  
Overlap Ratio ◽  
Three Dimensional Simulations

AbstractAn influence of the overlap on the performance of the Classical Savonius wind turbine was investigated. Unsteady two-dimensional numerical simulations were carried out for a wide range of overlap ratios. For selected configurations computation quality was verified by comparison with three-dimensional simulations and the wind tunnel experimental data available in literature. A satisfactory agreement was achieved. Power characteristics were determined for all the investigated overlap ratios for selected tip speed ratios. Obtained results indicate that the maximum device performance is achieved for the buckets overlap ratio close to 0.

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