scholarly journals Circuit Analysis and Optimization of GAA Nanowire FET Towards Low Power and High Switching

2021 ◽  
Author(s):  
V. Bharath Sreenivas ◽  
Vadthiya Narendar
Keyword(s):  
Low Power ◽  
Circuit Analysis ◽  
Device Performance ◽  
Gate Length ◽  
Subthreshold Slope ◽  
Cmos Inverter ◽  
Spacer Length ◽  
Drain Side ◽  
Optimal Values ◽  
Simulation Results

Abstract The main aim of this work is to study the effect of symmetric and asymmetric spacer length variations towards source and drain on n-channel SOI JL vertically stacked (VS) nanowire (NW) FET at 10 nm gate length (LG). Spacer length is proved to be one of the stringent metrics in deciding device performance along with width, height and aspect ratio (AR). The physical variants in this work are symmetric spacer length (LSD), source side spacer length (LS) and drain side spacer length (LD). The simulation results give highest ION/IOFF ratio with LD variation compared to LS and LSD, whereas latter two variations have similar effect on ION/IOFF ratio. At 25 nm (2.5 × LG) of LD, the device gives appreciable ON current with the highest ION/IOFF ratio (2.19 × 108) with optimum subthreshold slope (SS) and ensures low power and high switching drivability. Moreover, it is noticed that among optimal values of LS and LD, the device ION/IOFF ratio has an improvement of 22.69% as compared to other variations. Moreover, the effect of various spacer dielectrics on optimized device is also investigated. Finally, the CMOS inverter circuit analysis is performed on the optimized symmetric and asymmetric spacer lengths.

scholarly journals Sub-Threshold Slope and ON/OFF Current variation in Nano-Scale MOSFETs

2019 ◽  
Author(s):  
Raja N Mir
Keyword(s):  
Three Dimensional ◽  
Device Performance ◽  
Gate Length ◽  
Subthreshold Slope ◽  
Current Ratio ◽  
Nano Scale ◽  
Current Variation ◽  
Mos Device ◽  
Three Dimensional Simulations

The Multi Gate transistors (MGT) have been used to improve the transistor device performance at the nanometer scales. MGTs alleviate many problems in the planar devices due to tighter control of the gate on the channel. In this paper the change in the Fin Architecture and Gate Length of the MOS device, is correlated with the Subthreshold Slope (SS) and ON/OFF current ratio. The study is done by conducting experiments and three-dimensional simulations.

scholarly journals Effect of Oxide Thickness on GaN-based Double Gate MOSFETs

2020 ◽  
Vol 16 (2) ◽  
Author(s):  
Safayet Ahmed ◽  
Md. Tanvir Hasan
Keyword(s):  
Oxide Thickness ◽  
Device Performance ◽  
Gate Length ◽  
Double Gate ◽  
Short Channel Effects ◽  
Subthreshold Slope ◽  
Short Channel ◽  
Power Switching ◽  
Switching Device ◽  
Channel Effects

The effect of oxide thickness (EOT) on GaN-based double gate (DG) MOSFETs have been explored for low power switching device. The gate length (LG) of 8 nm with 4 nm underlap is considered. The device is turned off and on for gate voltage (VGS) of 0 V and 1 V, respectively. The effective oxide thickness (EOT) is varied from 1 nm to 0.5 nm and the device performance is evaluated. For EOT = 0.5 nm, the OFF-state current (IOFF), subthreshold slope (SS) and drain induced barrier lowering (DIBL) are obtained 2.97×10-8 A/μm, 69.67 mV/dec and 21.753 mV/V, respectively. These results indicate that, it is possible to minimize short channel effects (SCEs) by using smaller value of EOT.

AN EFFICIENT LOW-SWING MULTITHRESHOLD-VOLTAGE LOW-POWER DESIGN TECHNIQUE

2004 ◽  
Vol 13 (01) ◽  
pp. 193-203
Author(s):  
A. RJOUB ◽  
M. ALROUSAN ◽  
O. ALJARRAH ◽  
O. KOUFOPAVLOU
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Output Voltage ◽  
Supply Voltage ◽  
Low Power Design ◽  
Design Technique ◽  
Cmos Inverter ◽  
Spice Simulation ◽  
Comparison Results ◽  
Simulation Results

New low-power design architecture based on low-swing voltage technique is proposed in this paper. A new CMOS inverter of three output-voltage levels is used to achieve this target. To verify the validity of the proposed technique, three different logic families are used. SPICE simulation results for the three logic families show that more than 45% power dissipation can be saved, without sacrifice the speed operation. Comparison results between the proposed technique and other techniques based on low-swing voltage, shown the superiority of our technique in reducing the power dissipation. Based on 2.4 V supply voltage, a 16 * 16-bit multiplier is implemented by using the proposed technique in 0.25μm silicon technology.

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

scholarly journals Optimized Gateway Placement for Interference Cancellation in Transmit-Only LPWA Networks

Sensors ◽  
2018 ◽  
Vol 18 (11) ◽  
pp. 3884 ◽  
Author(s):  
Hongxian Tian ◽  
Mary Weitnauer ◽  
Gedeon Nyengele
Keyword(s):  
Low Power ◽  
Sensor Network ◽  
Interference Cancellation ◽  
Greedy Algorithms ◽  
Sensor Nodes ◽  
Wide Area ◽  
Delivery Ratio ◽  
Large Network ◽  
Packet Delivery ◽  
Simulation Results

We study the placement of gateways in a low-power wide-area sensor network, when the gateways perform interference cancellation and when the model of the residual error of interference cancellation is proportional to the power of the packet being canceled. For the case of two sensor nodes sending packets that collide, by which we mean overlap in time, we deduce a symmetric two-crescent region wherein a gateway can decode both collided packets. For a large network of many sensors and multiple gateways, we propose two greedy algorithms to optimize the locations of the gateways. Simulation results show that the gateway placements by our algorithms achieve lower average contention, which means higher packet delivery ratio in the same conditions, than when gateways are naively placed, for several area distributions of sensors.

scholarly journals Impact of Mole Fraction Variation on Nanoscale SiGe Hybrid FinFET on Insulator

2019 ◽  
Vol 8 (12S2) ◽  
pp. 61-66
Keyword(s):  
Band Gap ◽  
Mole Fraction ◽  
High Performance ◽  
Device Simulation ◽  
Channel Length ◽  
Gate Length ◽  
Electrical Characteristics ◽  
Simulation Results ◽  
High Performance Application ◽  
Device Modelling

This work investigates the performance of SiGe Hybrid JunctionLess FinFET (HJLFinFET) on insulator with different mole fraction x. The band gap difference for different mole fractions are explored. Impact of electrical characteristics and SCE of HJLFinFET are analyzed with fin width 10nm and varying gate length from 5nm-40nm for different mole fraction. Synopsys Sentaurus TCAD tool(sprocess and sdevice) are used in Device modelling and device simulation. Simulation results shows improvement in On current, DIBL and SS. For high performance application SiGe with mole fraction less than 0.3 at channel length less than 10nm are suitable because of the bandgap value is similar to silicon.

scholarly journals Effects of Doping Concentration on Device Performance of GaN-based Nano-regime MOSFETs

2017 ◽  
Vol 16 (1) ◽  
pp. 69-74
Author(s):  
Md Iktiham Bin Taher ◽  
Md. Tanvir Hasan
Keyword(s):  
Field Effect ◽  
Doping Concentration ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Device Performance ◽  
Gate Length ◽  
Drain Voltage ◽  
Switching Device ◽  
Device Applications

Gallium nitride (GaN) based metal-oxide semiconductor field-effect transistors (MOSFETs) are promising for switching device applications. The doping of n- and p-layers is varied to evaluate the figure of merits of proposed devices with a gate length of 10 nm. Devices are switched from OFF-state (gate voltage, VGS = 0 V) to ON-state (VGS = 1 V) for a fixed drain voltage, VDS = 0.75 V. The device with channel doping of 1×1016 cm-3 and source/drain (S/D) of 1×1020 cm-3 shows good device performance due to better control of gate over channel. The ON-current (ION), OFF-current (IOFF), subthreshold swing (SS), drain induce barrier lowering (DIBL), and delay time are found to be 6.85 mA/μm, 5.15×10-7 A/μm, 87.8 mV/decade, and 100.5 mV/V, 0.035 ps, respectively. These results indicate that GaN-based MOSFETs are very suitable for the logic switching application in nanoscale regime.

scholarly journals Simulation Study of the Use of AlGaN/GaN Ultra-Thin-Barrier HEMTs with Hybrid Gates for Achieving a Wide Threshold Voltage Modulation Range

Materials ◽  
2022 ◽  
Vol 15 (2) ◽  
pp. 654
Author(s):  
Shouyi Wang ◽  
Qi Zhou ◽  
Kuangli Chen ◽  
Pengxiang Bai ◽  
Jinghai Wang ◽  
...  
Keyword(s):  
Hole Concentration ◽  
Drain Current ◽  
Device Performance ◽  
Depletion Effect ◽  
Threshold Voltages ◽  
Gate Structure ◽  
Drain Side ◽  
Effective Reduction ◽  
Field Peak ◽  
Thin Barrier

In this work, novel hybrid gate Ultra-Thin-Barrier HEMTs (HG-UTB HEMTs) featuring a wide modulation range of threshold voltages (VTH) are proposed. The hybrid gate structure consists of a p-GaN gate part and a MIS-gate part. Due to the depletion effect assisted by the p-GaN gate part, the VTH of HG-UTB HEMTs can be significantly increased. By tailoring the hole concentration of the p-GaN gate, the VTH can be flexibly modulated from 1.63 V to 3.84 V. Moreover, the MIS-gate part enables the effective reduction in the electric field (E-field) peak at the drain-side edge of the p-GaN gate, which reduces the potential gate degradation originating from the high E-field in the p-GaN gate. Meanwhile, the HG-UTB HEMTs exhibit a maximum drain current as high as 701 mA/mm and correspond to an on-resistance of 10.1 Ω mm and a breakdown voltage of 610 V. The proposed HG-UTB HEMTs are a potential means to achieve normally off GaN HEMTs with a promising device performance and featuring a flexible VTH modulation range, which is of great interest for versatile power applications.

State-of-the-Art Master Slave Flip-Flop Designs for Low Power VLSI Systems

2016 ◽  
pp. 166-198
Author(s):  
Kunwar Singh ◽  
Satish Chandra Tiwari ◽  
Maneesha Gupta
Keyword(s):  
Low Power ◽  
State Of The Art ◽  
Relative Power ◽  
Power Budget ◽  
Comprehensive Overview ◽  
Feedback Strategy ◽  
Flip Flop ◽  
Simulation Results

This chapter presents a comprehensive overview of the conventional fully static master slave flip-flops used in low power VLSI systems where power budget is critical. In addition, the chapter also presents alternative realization of fully static master-slave flip-flops utilizing a modified feedback strategy. The flip-flops designed on the basis of modified architecture have been explained in detail and compared with state-of-the-art master slave flip-flop designs available in the literature. Extensive capacitance calculations have been performed in terms of clock load and capacitance at internal nodes has also been estimated for all the flip-flop configurations. This is executed in order to compare their relative power and delay characteristics which are well supported by simulation results.

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