Package Related Failure Mechanisms in Plastic BGA Packages Used for ASIC Devices

1996 ◽  
Author(s):  
K. Parekh ◽  
R. Milburn ◽  
K. Georgia
Keyword(s):  
Failure Analysis ◽  
Printed Circuit Board ◽  
Failure Mechanisms ◽  
Circuit Board ◽  
Physical Damage ◽  
Bga Packages ◽  
Plastic Surface ◽  
Bga Package ◽  
Bond Wires ◽  
Ball Bonds

Abstract This paper describes various package related failure mechanisms observed in the plastic surface mount Ball Grid Array (BGA) package. Two types of plastic BGA packages commonly known as 225 OMPAC™ (Over Molded Pad Array Carrier) and 225 GTPAC (Glob Top Pad Array Carrier) are covered in this paper. The GTPAC is not offered as a production package, but it is used for commercial prototypes and evaluations. The failure analysis results discussed in this paper are primarily of the devices which failed at different times during various reliability and qualification testing over a period of two years. The failure analysis results of field returns (about 10% of al the devices analyzed) from customers for the same period are also included in this study. Of all the devices in the BGA packages which were failure analyzed, about 50% lailed due to package related problems. All the package related failures fall into two major categories of failure mechanisms, package delamination and cracked open copper traces on the printed circuit board (PCB). The delamination resulted in a variety of physical damage such as lifted ball bonds at the die pads, fractured bond wires in the span as well as at the heel of the crescent bonds on the PCB substrate, and cracking of the encapsulant. The copper traces cracked from two types of stresses, mechanical and thermal. In addition, some of the techniques used for the failure analysis are briefly discussed in this paper.

Failure analysis on cracking of blind and buried vias of printed circuit board for high-end mobile phones

2019 ◽  
Vol 31 (4) ◽  
pp. 203-210
Author(s):  
Jie Tang ◽  
Yi Gong ◽  
Zhen-Guo Yang
Keyword(s):  
Failure Analysis ◽  
Mobile Phones ◽  
Printed Circuit Board ◽  
Failure Mechanisms ◽  
Performance Testing ◽  
Circuit Board ◽  
Chemical Compositions ◽  
Content Type ◽  
Printed Circuit ◽  
Prevention Methods

Purpose The submitted paper is mainly concerned with the cracking of blind and buried vias of printed circuit board (PCB) for smartphones which were encountered with abnormal display problems like scramble display or no display during service and had to be recalled. Design/methodology/approach To found out the root causes of this failure and dissolve this commercial dispute, comprehensive failure analysis was performed on the printed circuit board assemblies (PCBAs) and PCBs of the failed smartphone, such as macrograph and micrograph observation, chemical compositions analysis, thermal performance testing and blind via pull-off experiment, which finally helped to determine the causes. Besides that, the failure mechanisms were discussed in detail, and pertinent countermeasures were proposed point by point. Findings It was found that the PCB blind vias cracking was the main reason for the scramble display or no display of the smartphone, and the incomplete cleaning process before copper plating was the root cause of the blind vias cracking. Practical implications Achievement of this paper would not only help to provide the solid evidence for determining the responsibility of this commercial dispute but also lead to a better understanding of the failure mechanisms and prevention methods for similar failure cases of other advanced mobile phones. Originality/value Most failure analysis researches of PCBAs only focused on the unqualified products from manufacturing, while this paper addressed a failure analysis case of PCBAs products for smartphones from actual services, which was relatively rarely reported in the past.

In-Situ Mechanical Sample Preparation of Selected Sites and Components on Large Modules and Boards

2016 ◽  
Author(s):  
Jim Colvin ◽  
Timothy Hazeldine ◽  
Heenal Patel
Keyword(s):  
Sample Preparation ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Tilt Table ◽  
Standard Requirement ◽  
Open Design ◽  
Bga Packages ◽  
Silicon Thickness ◽  
Board Level

Abstract The standard requirement for FA Engineers needing to remove components from a board, prior to decapsulation or sample preparation, is shown to be greatly reduced, by the methods discussed here. By using a mechanical selected area preparation system with an open-design it is possible to reach all required areas of a large printed circuit board (PCB) or module to prepare a single component ‘in situ’. This makes subsequent optical or electrical testing faster and often more convenient to accomplish. Electronic End-pointing and 3D curvature compensation methods can often be used in parallel with sample prep techniques to further improve the consistency and efficacy of the decapsulation and thinning uniformity and final remaining silicon thickness (RST). Board level prep eliminates the worry of rework removal of BGA packages and the subsequent risk of damage to the device. Since the entire board is mounted, the contamination is restricted to the die surface and can be kept from the underside ball connections unlike current liquid immersion methods of package thinning or delayering. Since the camera is in line with the abrasion interface, imaging is real time during the entire milling and thinning process. Recent advances in automated tilt-table design have meant that a specific component’s angular orientation can be optimized for sample preparation. Improved tilt table technology also allows for improved mounting capability for boards of many types and sizes. The paper describes methods for decapsulation, thinning and backside polishing of a part ‘in situ’ on the polishing machine and allows the system to operate as a probe station for monitoring electrical characteristics while thinning. Considerations for designing board-level workholders are described – for boards that that are populated with components on one or even both sides. Using the techniques described, the quality of sample preparation and control is on a par with the processing of single package-level devices.

Reliability Failure Analysis of PCB and its Technological Improvement

2013 ◽  
Vol 401-403 ◽  
pp. 391-394 ◽  
Author(s):  
Li Fang Zhu
Keyword(s):  
Failure Analysis ◽  
Printed Circuit Board ◽  
Test Method ◽  
Circuit Board ◽  
Design And Technology ◽  
Thermal Shock Test ◽  
Shock Test ◽  
Technological Improvement ◽  
Electrical Interconnection ◽  
Improved Technology

Reliability failure analysis is extremely important in the manufacturing process of PCB (Printed Circuit Board). In this paper, we use thermal shock test method to analysis the electrical interconnection reliability of PCB in harsh environment. Also taking into account the reliability of PCB is closely related to its design and technology, approaches of technological improvement are proposed. Finally through temperature shock test method, the results show that the reliability of PCB designed with improved technology is enhanced.

scholarly journals Experiments and failure analysis of a charged board event on a hard disk drive printed circuit board assembly

2022 ◽  
Vol 115 ◽  
pp. 103657
Author(s):  
S. Chumpen ◽  
S. Pimpakun ◽  
B. Charoen ◽  
S. Pornnimitra ◽  
S. Plong-ngooluam ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Hard Disk Drive ◽  
Printed Circuit Board ◽  
Hard Disk ◽  
Disk Drive ◽  
Circuit Board ◽  
Printed Circuit Board Assembly ◽  
Printed Circuit ◽  
Circuit Board Assembly

Failure Analysis Techniques for Lead-Free Solder Joints

2005 ◽  
Author(s):  
Todd Castello ◽  
Dan Rooney ◽  
Dongkai Shangguan
Keyword(s):  
Failure Analysis ◽  
Printed Circuit Board ◽  
Failure Modes ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
Printed Circuit Board Assembly ◽  
Analysis Techniques ◽  
Solder Interconnects ◽  
Free Solder

Abstract Printed circuit board assembly with lead free solder is now a reality for most global electronics manufacturers. Extensive research and development has been conducted to bring lead free assembly processes to a demonstrated proficiency. Failure analysis has been an integral part of this effort and will continue to be needed to solve problems in volume production. Many failure analysis techniques can be directly applied to study lead free solder interconnects, while others may require some modification in order to provide adequate analysis results. In this paper, several of the most commonly applied techniques for solder joint failure analysis will be reviewed, including visual inspection, x-ray radiography, mechanical strength testing, dye & pry, metallography, and microscopy/photomicrography, comparing their application to lead bearing and lead free solder interconnects. Common failure modes and mechanisms will be described with examples specific to lead free solders, following PCB assembly as well as after accelerated reliability tests.

Development of Advanced Non Destructive Techniques for Failure Analysis of PCBs and PCBAs

2012 ◽  
Author(s):  
Julien Perraud ◽  
Shaïma Enouz-Vedrenne ◽  
Jean-Claude Clement ◽  
Arnaud Grivon
Keyword(s):  
Failure Analysis ◽  
Printed Circuit Board ◽  
Acoustic Microscopy ◽  
Circuit Board ◽  
Printed Circuit Board Assembly ◽  
X Ray ◽  
Printed Circuit ◽  
Advanced Analysis ◽  
Non Destructive ◽  
Non Destructive Techniques

Abstract The continuous miniaturization trends followed by a vast majority of electronic applications results in always denser PCBs (Printed Circuit Board) designs and PCBAs (Printed Circuit Board Assembly) with increasing solder joint densities. Current high-end designs feature high layer count sequential build-up PCBs with fine lines/spaces and numerous stacked filled microvias, as well as closely spaced BGA/QFN components with pitches down to 0.4mm. In recent years, several 3D packaging approaches have emerged to further increase system integration by enabling the stacking of several dies or packages. This has translated for example into the advent of highly integrated complex System in Package (SiP) modules, Package-on-Package (PoP) assemblies or chips embedded in PCBs [1]. From a failure analysis (FA) perspective, this deep technology evolution is setting extreme challenges for accurately locating a failure site, especially when destructive techniques are not desired. The few conventional non-destructive techniques like optical or x-ray inspection are now practically becoming useless for high density PCB designs. This paper reviews several advanced analysis techniques that could be used to overcome these limitations. It will be shown through several examples how three non-destructive methods usually dedicated to package analyses can be efficiently adapted to PCBs and PCBAs: • Scanning Acoustic Microscopy (SAM) • 3D X-ray Computed Tomography (CT) • Infrared Thermography A case study of a flex-rigid board FA is presented to show the efficiency of these three techniques over classical techniques. In this example, not only the defect localization has been possible, but also the defect characterization without using destructive analysis.

Flip-Chip Bump Interface Failure Mechanisms In Plastic BGA Packages and Failure Analysis Process Flow

2008 ◽  
Author(s):  
Zhaofeng Wang
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Failure Mechanisms ◽  
Integrity Test ◽  
Forming Process ◽  
Interface Failure ◽  
Process Flow ◽  
Analysis Process ◽  
Bga Packages ◽  
Intermittent Contact

Abstract The present paper studies several failure mechanisms at both UBM and Cu substrate side for flip-chip die open contact failures in multi-chip-module plastic BGA-LGA packages. A unique failure analysis process flow, starting from non-disturbance inspection of x-ray, substrate and die level C-SAM, bump x-section followed by a bump interface integrity test including under-fill etching and bump pull test and/or substrate etch has been developed. Four different types of failure mechanism in multiple chip module that are associated with open/intermittent contact, ranging from device layout design, UBM forming process defect, to assembly related bump-substrate interface delamination have been identified. The established FA process has been proved to be efficient and accurate with repeatable result. It has facilitated and accelarated new product qualification processes for a line of high power MCM modules.

Meander Delay Compensation in High-Speed Digital Multilayer Packages

2012 ◽  
Vol 2012 (1) ◽  
pp. 000334-000339 ◽  
Author(s):  
Robert Frye ◽  
Kai Liu
Keyword(s):  
High Speed ◽  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Propagation Time ◽  
Design Tools ◽  
Delay Compensation ◽  
Printed Circuit ◽  
Bga Packages ◽  
Timing Skew

The routing of multi-trace digital signal buses in printed circuit boards often results in mismatches in the lengths of the lines. This results in mismatched propagation time, referred to as “timing skew” in a digital system. A common method that is used to compensate for this is to add meander sections of line to lengthen the signal path length. Many advanced circuit board design tools have the capability to perform this compensation automatically. Advanced Ball Grid Array (BGA) packages are fabricated using fine-line multilayer laminate substrates or they are built up using multilayer wafer-scale processes. The design tools for these types of packages have evolved from printed circuit board tools and typically use the same methods and principles. It is very common in BGA packages for high-speed digital applications to use meander trace patterns to match the trace lengths of high speed bus interconnections either from the chip to the solder balls or between chips in a multi-chip package. However, electromagnetic simulation of these packages shows that despite the use of these techniques to match the physical length of the traces, electrical lengths often vary by as much as a factor of two. Examples of such packages are presented and analyzed. The resulting timing skew is not a significant problem in most current applications, since the overall delay is small compared with the clock interval. But with emerging applications pushing well beyond 10Gb/s, timing skew in packages will be an important consideration. The reasons for the ineffectiveness of meander delay compensation are discussed, and are demonstrated by some simple simulations.

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