Flip-Chip Bump Interface Failure Mechanisms In Plastic BGA Packages and Failure Analysis Process Flow

2008 ◽  
Author(s):  
Zhaofeng Wang
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Failure Mechanisms ◽  
Integrity Test ◽  
Forming Process ◽  
Interface Failure ◽  
Process Flow ◽  
Analysis Process ◽  
Bga Packages ◽  
Intermittent Contact

Abstract The present paper studies several failure mechanisms at both UBM and Cu substrate side for flip-chip die open contact failures in multi-chip-module plastic BGA-LGA packages. A unique failure analysis process flow, starting from non-disturbance inspection of x-ray, substrate and die level C-SAM, bump x-section followed by a bump interface integrity test including under-fill etching and bump pull test and/or substrate etch has been developed. Four different types of failure mechanism in multiple chip module that are associated with open/intermittent contact, ranging from device layout design, UBM forming process defect, to assembly related bump-substrate interface delamination have been identified. The established FA process has been proved to be efficient and accurate with repeatable result. It has facilitated and accelarated new product qualification processes for a line of high power MCM modules.

Failure Analysis Process Flows and Common Failure Mechanisms in Flip-Chip Packaged Device

2000 ◽  
Author(s):  
Steve Hsiung ◽  
Victer Chan
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Failure Mechanisms ◽  
Fault Identification ◽  
Process Flow ◽  
Packaging Technology ◽  
Root Cause ◽  
Analysis Process ◽  
Complex Construction ◽  
Non Destructive

Abstract With the increasing complexity of packaging technology, especially Flip-chip, package failure analysts face challenges to identify failure root cause. Due to the complex construction of Flip-chip packages, the conventional failure analysis process flow needs to be enhanced. Thus, generating a bench marked failure analysis process flow specifically for Flip-chip packaged devices becomes necessary. In this paper, the failure analysis process flow for Flip-chip package devices along with different failure mechanisms will be discussed and demonstrated. For instance, even in a simple continuity-open failure, instead of cross-sectioning the device as the initial fault identification step, the process flow details how to start from non-destructive C-SAM, TDR, to destructive die removal, polishing and finally cross-sectioning.

Infra-Red Reflectance Microscopy (IRRM) for Daisy Chain Flip Chip Device Failure Analysis

2004 ◽  
Author(s):  
Carlo Grilletto ◽  
Steve Hsiung ◽  
Andrew Komrowski ◽  
John Soopikian ◽  
Daniel J.D. Sullivan ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
State Of The Art ◽  
Failure Mechanisms ◽  
Simple Metal ◽  
X Ray ◽  
Infra Red ◽  
Cause Of Failure ◽  
Reflectance Microscopy ◽  
Ir Emission

Abstract This paper describes a method to "non-destructively" inspect the bump side of an assembled flip-chip test die. The method is used in conjunction with a simple metal-connecting "modified daisy chain" die and makes use of the fact that polished silicon is transparent to infra-red (IR) light. The paper describes the technique, scope of detection and examples of failure mechanisms successfully identified. It includes an example of a shorting anomaly that was not detectable with the state of the art X-ray equipment, but was detected by an IR emission microscope. The anomalies, in many cases, have shown to be the cause of failure. Once this has been accomplished, then a reasonable deprocessing plan can be instituted to proceed with the failure analysis.

Package Related Failure Mechanisms in Plastic BGA Packages Used for ASIC Devices

1996 ◽  
Author(s):  
K. Parekh ◽  
R. Milburn ◽  
K. Georgia
Keyword(s):  
Failure Analysis ◽  
Printed Circuit Board ◽  
Failure Mechanisms ◽  
Circuit Board ◽  
Physical Damage ◽  
Bga Packages ◽  
Plastic Surface ◽  
Bga Package ◽  
Bond Wires ◽  
Ball Bonds

Abstract This paper describes various package related failure mechanisms observed in the plastic surface mount Ball Grid Array (BGA) package. Two types of plastic BGA packages commonly known as 225 OMPAC™ (Over Molded Pad Array Carrier) and 225 GTPAC (Glob Top Pad Array Carrier) are covered in this paper. The GTPAC is not offered as a production package, but it is used for commercial prototypes and evaluations. The failure analysis results discussed in this paper are primarily of the devices which failed at different times during various reliability and qualification testing over a period of two years. The failure analysis results of field returns (about 10% of al the devices analyzed) from customers for the same period are also included in this study. Of all the devices in the BGA packages which were failure analyzed, about 50% lailed due to package related problems. All the package related failures fall into two major categories of failure mechanisms, package delamination and cracked open copper traces on the printed circuit board (PCB). The delamination resulted in a variety of physical damage such as lifted ball bonds at the die pads, fractured bond wires in the span as well as at the heel of the crescent bonds on the PCB substrate, and cracking of the encapsulant. The copper traces cracked from two types of stresses, mechanical and thermal. In addition, some of the techniques used for the failure analysis are briefly discussed in this paper.

Failure Analysis of Flip Chip C4 Package Using Focused Ion Beam Milling Technique

2011 ◽  
Author(s):  
Lihong Cao ◽  
Loc Tran ◽  
Wallace Donna
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Cross Sections ◽  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Failure Mechanisms ◽  
Organic Substrate ◽  
Dual Beam ◽  
Preparation Techniques

Abstract This article describes how Focused Ion Beam (FIB) milling methodology enhances the capability of package-level failure analysis on flip-chip packages by eliminating the artifacts induced by using conventional mechanical techniques. Dual- Beam Focused Ion Beam (DB FIB) cross sections were successful in detecting failure mechanisms related either to the die/C4 bump or package defect inside the organic substrate. This paper outlines detailed sample preparation techniques prior to performing the DB FIB cross-sections, along with case studies of DB FIB cross-sections.

Qualification of SiP Products: Quasi-Static Cyclic Mechanical Bending

2007 ◽  
Author(s):  
D. Farley ◽  
Y. Zhou ◽  
A. Dasgupta ◽  
J. F. J. Caers ◽  
J. W. C. de Vries
Keyword(s):  
Solder Joint ◽  
Failure Analysis ◽  
Failure Mode ◽  
Stress Testing ◽  
Flip Chip ◽  
Failure Mechanisms ◽  
Physics Of Failure ◽  
Static Mechanical ◽  
Mechanical Bending ◽  
Solder Joint Fatigue

An LGA (Land Grid Array) laminate-based epoxy-molded RF SiP (system-in-package) containing four wirebonded and three flip-chip dice is qualified for quasi-static mechanical flexure using a PoF (Physics-of-Failure) approach. The process includes: design and execution of accelerated stress testing; failure analysis to identify the failure mode and mechanism; and mechanistic simulations to assess acceleration factors for extrapolation of the failures to field environments for selected failure mechanisms. Illustrative qualification results are presented for solder joint fatigue.

System Failure Analysis Process and Case Study

2006 ◽  
Author(s):  
Nicholas Konkol
Keyword(s):  
Failure Analysis ◽  
Personal Computer ◽  
Failure Mechanisms ◽  
System Level ◽  
System Failure ◽  
Quality Improvements ◽  
Analysis Process ◽  
Electrical Overstress ◽  
Type Of Failure

Abstract Failure analysis at the system level requires a well-defined process and methodology in order to drive quality improvements onto motherboards or other subsystems of a personal computer. This process needs to be structured around the type of failure mechanisms that an FA group desires to understand. This paper discusses a specific case study involving electrical overstress in a personal computer that impacted the motherboard of the system. The case study resulted in a solution to increase quality on motherboards in the context of electrical overstress prevention.

Plastic BGA Module FA Process Flow Development

2002 ◽  
Author(s):  
Zhaofeng Wang ◽  
Lars Wagner ◽  
Chuan Cheah
Keyword(s):  
Failure Analysis ◽  
Multichip Module ◽  
Corrosion Mechanism ◽  
Front Side ◽  
Process Flow ◽  
Analysis Process ◽  
Flow Development ◽  
Die Attach

Abstract A failure analysis process flow development for a board mount plastic BGA multichip module is described. Both front and backside approaches are investigated. Following the probing (at both front and backside), front side chemical de-cap procedure is also developed to expose the components without disturbance. The development of this failure analysis process flow has successfully isolated defective IC dice, identified a die attach interface corrosion mechanism, and assembly related die top mechanical defects. This process can be adopted to failure analysis for other plastic BGA modules.

Novel Failure Analysis Sample Preparation Techniques for PoP Packaging

2012 ◽  
Author(s):  
Ng Sea Chooi ◽  
Chor Theam Hock ◽  
Ma Choo Thye ◽  
Khoo Poh Tshin ◽  
Dan Bockelman
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Failure Mechanisms ◽  
Preparation Process ◽  
Space Saving ◽  
Optical Probing ◽  
Preparation Techniques

Abstract Trends in the packaging of semiconductors are towards miniaturization and high functionality. The package-on-package(PoP) with increasing demands is beneficial in cost and space saving. The main failure mechanisms associated with PoP technology, including open joints and warpage, have created a lot of challenges for Assembly and Failure Analysis (FA). This paper outlines the sample preparation process steps to overcome the challenges to enable successful failure analysis and optical probing.

The Use of Precision Selective Area Milling for Failure Analysis of Flip-Chip Packages

2002 ◽  
Author(s):  
George F. Gaut
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Solder Bump ◽  
Selective Area ◽  
Fill Material ◽  
Solder Bumps ◽  
Time Required

Abstract Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.

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