Backside Etch: A New FA Technique for Gate Oxide Pinhole and Si Defect Identification for Power IC Devices

2001 ◽  
Author(s):  
Zhaofeng Wang
Keyword(s):  
Failure Mechanisms ◽  
Gate Oxide ◽  
Optical Microscope ◽  
Defect Identification ◽  
Typical Size ◽  
Oxide Defects ◽  
Power Ic

Abstract The present paper describes a backside F/A technique that identifies power IC devices’ Iqcc (quiescent Vcc current) failure mechanisms. Choline hydroxide[1, 2] is used to expose the entire die back, keeping gate oxide intact. The perspective gained from the backside etch allows an analyst to quantitatively observe gate oxide defects as well as Si defects. It is discovered that either one of them can cause the same Iqcc failure. More than 60 dice can be prepared on one specimen in 2-3 hrs. Another advantage of this technique over conventional top delayering or precision crosssection process is that no SEM work is necessary, only optical microscope is needed to identify defects with typical size of 0.1 μm.

Octahedral-Structured Gigantic Precipitates as the Origin of Gate-Oxide Defects in Metal-Oxide-Semiconductor Large-Scale-Integrated Circuits

1996 ◽  
Vol 35 (Part 1, No. 2B) ◽  
pp. 812-817 ◽  
Author(s):  
Manabu Itsumi ◽  
Hideo Akiya ◽  
Takemi Ueki ◽  
Masato Tomita ◽  
Masataka Yamawaki
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Large Scale ◽  
Gate Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Oxide Defects

The defect-centric perspective of device and circuit reliability—From gate oxide defects to circuits

2016 ◽  
Vol 125 ◽  
pp. 52-62 ◽  
Author(s):  
B. Kaczer ◽  
J. Franco ◽  
P. Weckx ◽  
Ph.J. Roussel ◽  
M. Simicic ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Circuit Reliability ◽  
Oxide Defects

Paper 4: Electron Optical Techniques of Failure Investigation

1969 ◽  
Vol 184 (2) ◽  
pp. 25-35 ◽  
Author(s):  
D. Scott ◽  
B. Loy ◽  
R. McCallum ◽  
G. H. Mills
Keyword(s):  
Failure Mechanisms ◽  
Optical Microscope ◽  
Surface Phenomena ◽  
Depth Of Focus ◽  
Optical Techniques ◽  
Fracture Surfaces ◽  
Failure Investigation ◽  
Non Destructive ◽  
Study Of Fracture Surfaces ◽  
Scanning Electron

Fractography, the study of fracture surfaces, is useful in failure investigations as the topography and characteristic markings of such surfaces are indicative of the mechanism of fracture which operated during the initiation of failure and crack propagation. Owing to the low depth of focus of the optical microscope, interpretation of some fracture surfaces may be difficult. The microscopic topography, and its relation to the causes and basic mechanisms of fracture, may be conveniently studied by electron microfractography using non-destructive replica methods. Replicas may be taken from selected areas of the fracture surface of large, unwieldy engineering components. Complementary electron optical techniques such as electron diffraction, scanning electron microscopy, and extraction replicas are used where possible to obtain additional fine-scale information of use in the elucidation of failure mechanisms. An explanation of the various techniques and examples of their use in the work of the National Engineering Laboratory in failure investigations is given. The investigations involve fatigue, brittle fracture, corrosion fatigue, stress corrosion, welding problems, and surface phenomena.

Effect of Negative Gate Bias on Single Pulse Avalanche Ruggedness of 1.2 kV Silicon Carbide MOSFETs

2018 ◽  
Vol 924 ◽  
pp. 735-738 ◽  
Author(s):  
Selamnesh Nida ◽  
Thomas Ziemann ◽  
Bhagyalakshmi Kakarla ◽  
Ulrike Grossner
Keyword(s):  
Silicon Carbide ◽  
Single Pulse ◽  
Gate Oxide ◽  
Gate Bias ◽  
Power Mosfets ◽  
Self Heating ◽  
Significant Difference ◽  
Oxide Defects ◽  
Voltage Spike ◽  
Avalanche Generation

When power MOSFETs experience a voltage spike initiating avalanche generation, a large amount of power is dissipated at the device junction. This leads to self-heating and lowers the threshold voltage. Some sources indicate that unintended opening of the channel creates a positive feedback, thereby increasing heat generation and leading to thermal runaway. Therefore, keeping MOSFETs off by applying a negative gate bias should improve avalanche ruggedness. In this report, this claim is investigated by comparing single pulse avalanche ruggedness of commercial 1.2 kV, 80 mΩ planar and trench MOSFETs at -10 V and 0 V off-state gate bias. Both planar and trench devices show a small increase in their breakdown voltage with negative gate bias. However, there is no significant difference in avalanche withstanding energy. Even in investigated trench gate devices where the gate oxide is susceptible to interface as well as oxide defects, keeping the gate voltage at VGS = -10 V did not result in improvements in ruggedness.

An Application of a Nanoprobe Technique in the Characterization of Advanced SRAM Devices

2008 ◽  
Author(s):  
Hung-Sung Lin ◽  
Chun-Ming Chen
Keyword(s):  
Barrier Layer ◽  
Gate Oxide ◽  
Active Area ◽  
Technology Node ◽  
Channel Gate ◽  
Oxide Defects ◽  
Contact Barrier

Abstract The importance of understanding mismatched behavior in SRAM devices has increased as the technology node has shrunk below 100nm. Using the nanoprobe technique [1-3], the MOS characteristics of failure bits in actual SRAM cells have been directly measured. After transistors that are failing were identified, the best approach for identifying nanoscale defects was determined. In this study, several types of nanoscale defects, such as offset spacer residue, salicide missing from the active area, doping missing from the channel, gate oxide defects, contact barrier layer residue, and severed poly-gate silicide were successfully discovered.

TEM Direct Observation of Gate Oxide Defects

2002 ◽  
Author(s):  
Nathan Wang ◽  
Sabbas Daniel
Keyword(s):  
Direct Observation ◽  
Three Dimensional ◽  
Final Analysis ◽  
Gate Oxide ◽  
Cross Sectional ◽  
Electrical Test ◽  
Wet Chemical ◽  
Oxide Defects ◽  
Oxide Damage

Abstract This paper describes the FA technique to identify very tiny defects that cause gate oxide damage. These defects as examples include crystal originated pits, gate oxide pinhole and residual. The defects may have the same electrical signature; the same kind of in gate oxide will be seen when the sample is simply deprocessed with wet chemical and observed with SEM; but they are distinctly different mechanisms. Electrical test, emission microscope, FIB and SEM were used to localize the defect and TEM for the final analysis. The application of planeview, cross-sectional and three-dimensional TEM is discussed.

The behaviour of radiation-induced gate-oxide defects in MOSFETs during annealing at 140°C

1998 ◽  
Vol 240 (1-3) ◽  
pp. 182-192 ◽  
Author(s):  
M. Pejović ◽  
A. Jakšić ◽  
G. Ristić
Keyword(s):  
Gate Oxide ◽  
Radiation Induced ◽  
Oxide Defects

scholarly journals Effect of Gate Oxide Defects on Tunnel Transistor RF Performance

2018 ◽  
Author(s):  
M. Hellenbrand ◽  
E. Memisevic ◽  
J. Svensson ◽  
A. Krishnaraja ◽  
E. Lind ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Oxide Defects ◽  
Tunnel Transistor ◽  
Rf Performance
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