Effect of Negative Gate Bias on Single Pulse Avalanche Ruggedness of 1.2 kV Silicon Carbide MOSFETs

When power MOSFETs experience a voltage spike initiating avalanche generation, a large amount of power is dissipated at the device junction. This leads to self-heating and lowers the threshold voltage. Some sources indicate that unintended opening of the channel creates a positive feedback, thereby increasing heat generation and leading to thermal runaway. Therefore, keeping MOSFETs off by applying a negative gate bias should improve avalanche ruggedness. In this report, this claim is investigated by comparing single pulse avalanche ruggedness of commercial 1.2 kV, 80 mÎ© planar and trench MOSFETs at -10 V and 0 V off-state gate bias. Both planar and trench devices show a small increase in their breakdown voltage with negative gate bias. However, there is no significant difference in avalanche withstanding energy. Even in investigated trench gate devices where the gate oxide is susceptible to interface as well as oxide defects, keeping the gate voltage at VGS = -10 V did not result in improvements in ruggedness.

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Reliability and Ruggedness of Planar Silicon Carbide MOSFETs

Materials Science Forum ◽

10.4028/www.scientific.net/msf.963.782 ◽

2019 ◽

Vol 963 ◽

pp. 782-787

Author(s):

Kevin Matocha ◽

In Hwan Ji ◽

Sauvik Chowdhury

Keyword(s):

Silicon Carbide ◽

Threshold Voltage ◽

Dielectric Breakdown ◽

Gate Oxide ◽

Time Dependent ◽

Gate Bias ◽

Constant Voltage ◽

Time Dependent Dielectric Breakdown ◽

Planar Silicon ◽

State Of Art

The reliability and ruggedness of Monolith/Littelfuse planar SiC MOSFETs have been evaluated using constant voltage time-dependent dielectric breakdown for gate oxide wearout predictions, showing estimated > 100 year life at VGS=+25V and T=175C. Using extended time high-temperature gate bias, we have shown < 250 mV threshold voltage shifts for > 5000 hours under VGS=+25V and negligible threshold voltage shifts for > 2500 hours under VGS=-10V, both at T=175C. Under unclamped inductive switching, these 1200V, 80 mOhm SiC MOSFETs survive 1000 mJ of avalanche energy, meeting state-of-art ruggedness for 1200V SiC MOSFETs.

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Design and Process Issues for Silicon Carbide Power DiMOSFETS

MRS Proceedings ◽

10.1557/proc-640-h4.5 ◽

2000 ◽

Vol 640 ◽

Cited By ~ 2

Author(s):

Sei-Hyung Ryu ◽

Anant K. Agarwal ◽

Nelson S. Saks ◽

Mrinal K. Das ◽

Lori A. Lipkin ◽

...

Keyword(s):

Silicon Carbide ◽

Drain Current ◽

Gate Oxide ◽

Channel Structure ◽

Channel Mobility ◽

Power Mosfets ◽

Buried Channel ◽

P Type ◽

Very High ◽

Effective Channel

ABSTRACTThis paper discusses the design and process issues of high voltage power DiMOSFETs (Double implanted MOSFETs) in 4H-silicon carbide (SiC). Since Critical Field (EC) in 4H-SiC is very high (10X higher than that of a Si), special care is needed to protect the gate oxide. 2D device simulation tool was used to determine the optimal JFET gap, which provides adequate gate oxide protection as well as a reasonable JFET resistance. The other issue in 4H-SiC DiMOSFETs is extremely low effective channel mobility (μeff) in the implanted p-well regions. NO anneal of the gate oxide and buried channel structure are used for increasing μeff. NO anneal, which was reported to be very effective in increasing the μeff of SiC MOSFETS in p-type epilayers, did not produce reasonable μeff of SiC MOSFETs in the implanted p-well. Buried channel (BC) structure with 2.7×1012 cm−2 charge in the channel showed high μeff utilizing bulk buried channel, but resulted in a normally-on device. However, it was shown that by controlling the charge in the BC layer, a normally off device with high μeff can be produced. A 3.3 mm × 3.3 mm DiMOSFET with BC structure showed a drain current of 10 A, which is the highest current reported in SiC power MOSFETs to date, at a forward drop of 4.4 V with a gate bias of only 2.5 V.

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Integrated ESD Robustness through Device Analysis of Ultra-Small Low Voltage Power MOSFETs

ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2014p0350 ◽

2014 ◽

Author(s):

Ian Kearney ◽

Hank Sung

Keyword(s):

New Product Development ◽

Silicon Oxide ◽

Low Voltage ◽

Photon Emission ◽

Electrical Characterization ◽

Power Mosfets ◽

Low Leakage ◽

A Cell ◽

Thermographic Analysis ◽

Voltage Spike

Abstract Low voltage power MOSFETs often integrate voltage spike protection and gate oxide ESD protection. The basic concept of complete-static protection for the power MOSFETs is the prevention of static build-up where possible and the quick, reliable removal of existing charges. The power MOSFET gate is equivalent to a low voltage low leakage capacitor. The capacitor plates are formed primarily by the silicon gate and source metallization. The capacitor dielectric is the silicon oxide gate insulation. Smaller devices have less capacitance and require less charge per volt and are therefore more susceptible to ESD than larger MOSFETs. A FemtoFETTM is an ultra-small, low on-resistance MOSFET transistor for space-constrained handheld applications, such as smartphones and tablets. An ESD event, for example, between a fingertip and the communication-port connectors of a cell phone or tablet may cause permanent system damage. Through electrical characterization and global isolation by active photon emission, the authors identify and distinguish ESD failures. Thermographic analysis provided additional insight enabling further separation of ESD failmodes. This paper emphasizes the role of failure analysis in new product development from the create phase through to product ramp. Coupled with device electrical simulation, the analysis observations led to further design enhancement.

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